Clock Bias Adjustment Circuit for Independent Edge Timing
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Solution Overview
Problem
Conventional clock paths in semiconductor devices face challenges with high power consumption and limited delay range due to variable load capacitors and current generators, which require multiple stages to achieve suitable delay ranges and fine delay steps, making it difficult to control timing accurately and efficiently.
Innovation Solution
A clock signal adjustment circuit with multiple series-connected stages, each with a voltage generator and select circuit to provide tap voltages as bias voltages for transistors, allowing independent control of rising and falling edges of clock signals, reducing the number of stages needed and thus lowering power consumption while improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If variable load capacitors are used to adjust clock signal timing, then delay range is provided, but power consumption increases and delay range is limited by process and temperature variations
Solution Approach 1:
The patent changes the control parameter from capacitor value (which has limited adjustability and high power consumption) to transistor width parameters (W0, W1, W2, W3) that can be precisely controlled during manufacturing. This allows continuous adjustment of delay time through parameter variations without the power penalties of conventional capacitor-based approaches.
Solution Approach 2:
The delay adjustment is segmented into multiple independent controllable stages, each with its own transistor pairs (M0a/M1a, M2a/M3a, etc.). Each stage can be independently adjusted by controlling the width of specific transistors, allowing fine-grained timing control with lower power consumption compared to a single large capacitor approach.
2Adaptability or versatility
If multiple stages are used in delay line to obtain suitable delay range, then delay range is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple delay adjustment functions into a unified circuit structure where transistor width control simultaneously provides both delay range adjustment and fine delay step control. The combined effect of parallel transistor pairs with different width ratios achieves wide delay range without requiring cascading multiple high-power delay stages.
3Manufacturing precision
If variable current generator is used to correct duty cycle, then duty cycle correction is achieved, but current consumption increases
Solution Approach 1:
The patent uses transistor width parameters to control both delay and duty cycle correction, replacing current-based control with voltage-based control through the transistor gate. This parameter change allows precise duty cycle adjustment without the high current consumption inherent in conventional current generator approaches.
Data Source
AI summary
Some embodiments include apparatuses comprising a first node; a second node; a first transistor and a second transistor, the first and second transistors including a common gate coupled to the node and a common terminal coupled to the second node; first additional transistors coupled in parallel with each other between a terminal of the first transistor and a first supply node, the first additional transistors including gates; and second additional transistors coupled in parallel with each other between a terminal of the second transistor and a second supply node, the second additional transistors including gates.