Clock Distribution Bias Segmentation for Signal Quality and Power

Solution Overview

Problem

In semiconductor devices, controlling bias voltages for logic circuits is inefficient, leading to degraded clock signaling characteristics and unnecessary power consumption due to uniform bias voltage levels across different circuit regions.

Innovation Solution

A clock distribution circuit that independently controls bias voltages for different circuits, allowing separate bias voltage levels for circuits transferring signals through global lines and those directly coupled to global lines, optimizing power efficiency and signal quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If uniform bias voltage is applied to all logic circuits, then device complexity is reduced and ease of manufacture is improved, but power consumption increases and clock signaling characteristics deteriorate

Engineering Contradiction:

Improveease of manufactureVSAvoidpower consumption

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The bias voltage control system is segmented into multiple independent control paths. First bias voltage is generated for circuits directly coupled to global lines, while second bias voltage is generated for circuits transferring signals through global lines. This segmentation allows each circuit region to receive optimized bias voltage independently, reducing overall power consumption while maintaining manufacturing simplicity through standardized voltage generation circuits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different bias voltage levels are applied to different circuit regions based on their specific functional requirements. Circuits directly coupled to global lines receive first bias voltage optimized for their switching characteristics, while circuits using global lines for signal transfer receive second bias voltage optimized for signal integrity. This local quality approach reduces power consumption in each region without compromising overall device performance.

Inventive Principle:

Principle #3Local quality

2Device complexity

If uniform bias voltage is applied to all logic circuits, then device complexity is reduced, but clock signaling characteristics deteriorate

Engineering Contradiction:

Improvedevice complexityVSAvoidclock signaling characteristics

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The bias voltage control system is segmented into multiple independent control paths. First bias voltage is generated for circuits directly coupled to global lines, while second bias voltage is generated for circuits transferring signals through global lines. This segmentation allows each circuit region to receive optimized bias voltage independently, reducing overall power consumption while maintaining manufacturing simplicity through standardized voltage generation circuits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different bias voltage levels are applied to different circuit regions based on their specific functional requirements. Circuits directly coupled to global lines receive first bias voltage optimized for their switching characteristics, while circuits using global lines for signal transfer receive second bias voltage optimized for signal integrity. This local quality approach reduces power consumption in each region without compromising overall device performance.

Inventive Principle:

Principle #3Local quality

3Reliability

If higher bias voltage is applied to improve clock signaling characteristics, then signal quality improves, but power consumption increases

Engineering Contradiction:

Improveclock signaling characteristicsVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

Different bias voltage levels are applied to different circuit regions based on their specific functional requirements. Circuits directly coupled to global lines receive first bias voltage optimized for their switching characteristics, while circuits using global lines for signal transfer receive second bias voltage optimized for signal integrity. This local quality approach reduces power consumption in each region without compromising overall device performance.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The bias voltage parameter is changed and optimized for different circuit regions. By adjusting the bias voltage level specifically for circuits directly coupled to global lines versus circuits transferring signals through global lines, the system achieves optimal clock signaling characteristics in each region while minimizing overall power consumption through parameter differentiation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11385674B2Clock distribution circuit and semiconductor device including the clock distribution circuit

Publication Date: 2022.07.12 SK HYNIX INC

AI summary

A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.