Clock Boosting via General Routing Network in PLDs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock boosting techniques for programmable logic devices (PLDs) require additional hardware components, increasing manufacturing costs and silicon area, and reducing logic density.
Innovation Solution
Software clock boosting techniques that utilize unused general routing resources within the PLD to introduce optimal clock skews without additional hardware, by modifying the current route to insert unused wires into the clock distribution network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock boosting techniques are used with additional hardware components, then clock skew can be introduced to increase timing margins, but manufacturing costs increase and silicon area increases
Solution Approach 1:
The general routing network is designed to serve dual purposes: routing data signals between logic blocks and routing clock signals to registers. By making the routing infrastructure universal, the patent eliminates the need for dedicated hardware components for clock boosting, thereby avoiding additional silicon area while still achieving the required clock skew for improved timing margins
Solution Approach 2:
The system uses its own existing general routing resources to provide clock boosting functionality. Instead of requiring external or additional specialized hardware, the PLD leverages its existing routing infrastructure to introduce clock skew, making the system self-sufficient and avoiding additional manufacturing costs and silicon area
2Reliability
If conventional clock boosting techniques are used with additional hardware components, then clock skew can be introduced to increase timing margins, but manufacturing costs increase
Solution Approach 1:
The general routing network is designed to serve dual purposes: routing data signals between logic blocks and routing clock signals to registers. By making the routing infrastructure universal, the patent eliminates the need for dedicated hardware components for clock boosting, thereby avoiding additional manufacturing costs while still achieving the required clock skew for improved timing margins
Solution Approach 2:
The system uses its own existing general routing resources to provide clock boosting functionality. Instead of requiring external or additional specialized hardware, the PLD leverages its existing routing infrastructure to introduce clock skew, making the system self-sufficient and avoiding additional manufacturing costs
3Reliability
If conventional clock boosting techniques are used with additional hardware components, then clock skew can be introduced to increase timing margins, but logic density decreases
Solution Approach 1:
The general routing network is designed to serve dual purposes: routing data signals between logic blocks and routing clock signals to registers. By making the routing infrastructure universal, the patent eliminates the need for dedicated hardware components for clock boosting, thereby maintaining logic density while still achieving the required clock skew for improved timing margins
Solution Approach 2:
The system uses its own existing general routing resources to provide clock boosting functionality. Instead of requiring external or additional specialized hardware, the PLD leverages its existing routing infrastructure to introduce clock skew, maintaining device complexity at acceptable levels
4Productivity
If general routing wires are inserted into clock distribution network, then maximum frequency can be improved by up to 13%, but clock distribution complexity increases
Solution Approach 1:
The general routing network is designed to serve dual purposes: routing data signals between logic blocks and routing clock signals to registers. By making the routing infrastructure universal, the patent achieves improved maximum frequency (up to 13%) while avoiding additional clock distribution complexity, as the same general routing infrastructure is already present in the device
Solution Approach 2:
The system dynamically configures the general routing network to serve as clock distribution paths when needed. The routing resources can be reconfigured via programming to provide clock skew adjustments, allowing the system to adapt its behavior based on timing requirements without permanent hardware modifications
Data Source
AI summary
In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a plurality of routing wires and a clock distribution network having a plurality of routing wires. At least one clock signal path is provided within the PLD from a clock source to one of the registers via a routing wire of the clock distribution network and a routing wire of the general routing network.