Clock Distribution Network With Boosting Stages for RC Attenuation

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Solution Overview

Problem

In high-speed computer systems, the transmission of clock signals over long distances within semiconductor apparatuses results in reduced amplitude and increased load, leading to inefficiencies due to RC attenuation, which affects synchronization and data transfer reliability.

Innovation Solution

A clock distribution network is implemented with multiple boosting circuits and drivers to amplify and shift voltage levels of clock signals, ensuring sufficient amplitude and minimizing delay and skew across internal circuits, using a combination of global and local drivers and converters to maintain signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the clock transmission line becomes longer to transfer the clock signal to a great number of internal circuits, then the coverage of clock signal distribution is improved, but the amplitude of the clock signal becomes smaller due to RC attenuation

Engineering Contradiction:

Improvecoverage area of clock distributionVSAvoidamplitude of clock signal

Core Design Contradiction:

Area of stationary objectVSStrength

Solution Approach 1:

The patent divides the clock distribution network into multiple segments with intermediate boosting circuits. Each segment has its own driver and boosting circuit, breaking the long transmission line into shorter segments. This segmentation allows each segment to maintain adequate signal amplitude while collectively covering a larger area, resolving the contradiction between distribution coverage and signal strength.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces boosting circuits as intermediary elements between the clock driver and internal circuits. These boosting circuits actively regenerate and amplify the clock signal at intermediate points, compensating for RC attenuation along the transmission line. The intermediary boosting circuits maintain signal amplitude despite increased transmission distance, enabling both large coverage and strong signal strength.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Power

If a CML driver with more powerful driving force is used, then the driving capability is improved, but the current consumption becomes greater

Engineering Contradiction:

Improvedriving force of CML driverVSAvoidcurrent consumption of CML driver

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The patent segments the driving function across multiple drivers and boosting circuits rather than relying on a single powerful CML driver. Each driver and boosting circuit operates at moderate power levels, collectively providing the necessary driving force while distributing the current consumption across multiple components, reducing the burden on any single element and lowering overall power inefficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The boosting circuits are designed to automatically detect and amplify weak clock signals without requiring a powerful CML driver. Each boosting circuit monitors its input signal and self-regulates its amplification to maintain adequate amplitude, eliminating the need for an over-powered driver and reducing unnecessary current consumption.

Inventive Principle:

Principle #25Self-service

3Quantity of substance

If the transmission line becomes longer, then the number of internal circuits served is improved, but the synchronization accuracy deteriorates due to increased phase differences

Engineering Contradiction:

Improvenumber of internal circuits servedVSAvoidsynchronization accuracy

Core Design Contradiction:

Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent segments the clock distribution into multiple zones, each with its own driver and boosting circuit. This segmentation ensures that each segment has limited length and controlled phase delay, maintaining synchronization accuracy within each segment. The coordinated operation of multiple segments allows serving a large number of internal circuits while keeping phase differences within acceptable limits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The boosting circuits provide feedback mechanisms to detect phase differences and signal degradation in real-time. By monitoring the clock signal characteristics and adjusting amplification accordingly, the feedback system compensates for phase delays introduced by longer transmission lines, maintaining synchronization accuracy across a large number of served circuits.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20220029611A1Clock distribution network, a semiconductor apparatus and a semiconductor system using the same

Publication Date: 2022.01.27 SK HYNIX INC

AI summary

A clock distribution network includes a global driver configured to receive a pair of clock signals to generate a pair of global clock signals, a clock transmission driver configured to amplify the pair of global clock signals to generate a pair of transmission clock signals, a first boosting circuit configured to boost voltage levels of the pair of transmission clock signals to generate a pair of first boosted clock signals, a first local driver configured to shift voltage levels of the pair of first boosted clock signals to generate a pair of first local clock signals, a second boosting circuit configured to boost voltage levels of the pair of first boosted clock signals to generate a pair of second boosted clock signals, and a second local driver configured to shift voltage levels of the pair of second boosted clock signals to generate a pair of second local clock signals.