Clock Boundary Spreader for Mesochronous SoC Communication
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Solution Overview
Problem
Current communication techniques between different clock domains in System-on-Chip (SoC) face challenges in achieving efficient communication without clock balancing, leading to bandwidth limitations and increased complexity, especially as the number of clock domains increases in deep sub-micron technologies.
Innovation Solution
The proposed solution involves a Clock Boundary Spreader (CBS) mechanism that merges synchronization and mesochronous techniques, allowing for communication between remote clock domains without clock balancing, using shared hardware resources and a shared response buffer to implement optimized links suitable for Network on Chip (NoC) architecture, enabling high-frequency operation and reducing bandwidth limitations and wire overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronizers are used to cross clock boundaries, then communication between clock domains is enabled, but clock signals have to be distributed and balanced which increases complexity and is not feasible for remote clock domains
Solution Approach 1:
The patent extracts the clock balancing requirement from the communication mechanism by using asynchronous FIFOs that operate independently of clock synchronization. The write pointer in the first clock domain and read pointer in the second clock domain are decoupled, eliminating the need for clock signal distribution and balancing between remote domains.
Solution Approach 2:
The patent introduces an intermediary asynchronous FIFO buffer between remote clock domains that mediates data transfer without requiring direct clock synchronization. The FIFO acts as a buffer that absorbs clock domain differences, allowing reliable communication without complex clock distribution infrastructure.
2Measurement precision
If Gray coded pointers are used to avoid wrong sampling, then pointer synchronization is improved, but the pointers must be placed in the same physical cluster which limits clock domain placement flexibility
Solution Approach 1:
The patent segments the pointer synchronization into two independent parts: write pointer generation in the first clock domain and read pointer generation in the second clock domain. Each pointer operates independently in its own clock domain without requiring physical co-location, enabling flexible placement of clock domains while maintaining accurate pointer sampling through independent Gray encoding in each domain.
3Adaptability or versatility
If 4-phases asynchronous communication is used, then communication between remote clock domains is enabled, but bandwidth is heavily limited which does not meet high performance requirements
Solution Approach 1:
The patent uses full parallel pointers (non-Gray coded) copied to both clock domains independently, allowing wide data buses to be transferred simultaneously. This copying approach enables high-bandwidth communication by transferring multiple data bits in parallel without the bandwidth limitations of phased asynchronous protocols.
4Adaptability or versatility
If clock domains are placed in large regions to respect maximum clock skew, then more clock domains can be included, but clock tree balancing becomes a heavy task requiring significant time and effort
Solution Approach 1:
The patent extracts the clock skew constraint from the system design by using asynchronous communication mechanisms that are inherently immune to clock skew. This allows clock domains to be placed anywhere on the chip without requiring timing closure efforts for clock tree balancing, significantly reducing design time and effort.
Data Source
AI summary
Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.