Clock Buffer Pair Bulk-Voltage Control for Low-Jitter Distribution
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Solution Overview
Problem
Current clock distribution circuitry faces challenges in accurately transmitting clock signals with high speed and low power consumption, especially as semiconductor devices miniaturize and energy efficiency becomes a priority, while maintaining precise duty cycle, slew, and delay adjustments.
Innovation Solution
The proposed clock distribution circuitry employs a configuration of inverting buffers with control circuitry generating variable control signals to dynamically adjust duty cycle, slew, and delay of clock signals, using only four independently controllable signals, and incorporates cross-coupled inverters to maintain signal quality and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock distribution circuitry operates at higher speeds with miniaturized devices, then productivity and integration density improve, but maintaining accuracy and low power consumption becomes more difficult
Solution Approach 1:
The patent implements dynamic control of buffer circuitry parameters through control signals that adjust the operating characteristics of buffers in the clock distribution network. This allows the system to adapt buffer strength, delay, and power consumption in real-time to maintain clock signal accuracy despite variations in operating conditions, device miniaturization, and temperature changes.
2Productivity
If clock distribution circuitry operates at higher speeds, then productivity improves, but power consumption increases
Solution Approach 1:
The control circuitry dynamically adjusts the power consumption of buffer stages based on the required clock signal speed and distribution requirements. By selectively activating or deactivating buffer stages and adjusting their operating points, the system can achieve high-speed operation when needed while consuming minimal power during normal operation, thus resolving the contradiction between speed and power consumption.
3Manufacturing precision
If more control signals are used to adjust duty cycle, slew, and delay, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent employs a set of control signals that serve multiple functions simultaneously. The same control signals that adjust the duty cycle of clock signals also influence slew rate and delay characteristics. This multi-functionality allows precise control of multiple clock signal properties without proportionally increasing the number of control signals, thus maintaining manufacturing precision while limiting device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise adjustments to clock signal properties, reduces processing burden, and minimizes jitter by controlling bulk voltages, achieving accurate clock signal transmission with reduced power consumption and noise, thus addressing the challenges of high-speed and low-power operation.
Implementation Method 1
the first buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the first control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the second control signal
Data Source
Figure 1
Figure 2A~2B
Figure 3~4
AI summary
Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals, wherein: the first buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the first control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the second control signal; the second buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the third control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the fourth control signal; one of the first buffers and one of the second buffers are connected in series as a first buffer pair to form a first clock path for propagation of a clock signal therealong in a propagation direction; another one of the first buffers and another one of the second buffers are connected in series as a second buffer pair to form a second clock path for propagation of a clock signal therealong in the propagation direction; and the control circuitry is configured to control at least one of the first to fourth control signals as a variable signal.