AC-Coupled Clock Buffer Chain for Duty Cycle Control
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Solution Overview
Problem
Clock distribution circuitry faces challenges in maintaining accurate duty cycle control for clock signals, especially in high-speed and low-power semiconductor applications, where existing solutions struggle to ensure precise duty cycle accuracy and energy efficiency.
Innovation Solution
The proposed solution involves a clock distribution circuitry with a series of buffers connected via AC coupling capacitors and control circuitry that applies DC bias signals to adjust the duty cycle of clock signals, using measurement signals and reference signals to control the output duty cycle, allowing for precise adjustment during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock distribution circuitry operates at higher speeds with miniaturised semiconductor devices, then productivity and integration density are improved, but maintaining accurate duty cycle control becomes more difficult and power consumption increases
Solution Approach 1:
The patent implements a feedback control system where the duty cycle of the output clock signal is measured and compared against a target duty cycle, and the difference is used to adjust DC bias signals applied to buffers along the clock path. This closed-loop feedback mechanism enables accurate duty cycle control even at high clock speeds and in miniaturised semiconductor devices where process variations and signal degradation would otherwise make precision control difficult.
2Manufacturing precision
If duty cycle control is implemented through multiple buffers with DC bias adjustment, then manufacturing precision of duty cycle is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by introducing DC bias adjustment specifically at buffer stages along the clock distribution path where duty cycle distortion occurs. Rather than redesigning the entire clock distribution system, the invention selectively modifies specific locations (buffer inputs) with duty cycle correction circuitry. This localized approach improves duty cycle accuracy while minimizing overall device complexity by leaving the rest of the clock distribution architecture unchanged.
3Adaptability or versatility
If AC coupling capacitors are used to isolate DC levels between buffers, then adaptability of clock distribution is improved, but loss of information about duty cycle occurs
Solution Approach 1:
The patent introduces DC bias signals as intermediary control voltages applied to the inputs of buffers along the clock path. These DC bias signals act as mediators that compensate for the information loss caused by AC coupling capacitors. By adjusting the DC bias at each buffer stage, the system can restore and maintain the correct duty cycle even though the AC coupling blocks direct DC level transmission between buffers.
Data Source
AI summary
Clock distribution circuitry configured for duty cycle control, the circuitry comprising: a plurality of buffers connected in series along a clock path, each of the buffers having an input terminal and an output terminal, the input terminal being connected to the clock path via a corresponding AC coupling capacitor, and the clock, path configured to receive an input clock signal at its input node and output an output clock signal at its output node, the output clock signal having an output duty cycle; and control circuitry connected to apply a DC bias signal to the input terminal of each of the plurality of buffers, wherein the control circuitry is configured to: obtain a measurement signal indicative of the output duty cycle; and control the DC bias signals, based on a difference between the measurement signal and a reference signal, so as to control the output duty cycle.