Input Clock Buffer with Capacitive Coupling for Duty Ratio Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional input clock buffers face inaccuracies in output clock signal duty ratio when one input terminal is coupled to a predetermined voltage level or experiences non-desired DC level variations of the input signal.
Innovation Solution
An input clock buffer comprising capacitors, amplifiers, a frequency detection circuit, and a switch that forms signal paths and generates output signals while filtering DC components and adjusting coupling based on frequency detection signals to maintain accurate duty ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one input terminal is coupled to a predetermined voltage level or DC level varies, then the circuit structure is simplified, but the duty ratio accuracy deteriorates
Solution Approach 1:
The patent introduces capacitors as intermediary elements to couple the differential input signal to the amplifier inputs. These capacitors block DC components while allowing AC clock signals to pass, thereby eliminating the need to directly couple one input terminal to a predetermined voltage level. This intermediary approach maintains accurate duty ratio by preventing DC level variations from affecting the amplifier operation, while still providing a simplified circuit structure compared to more complex DC compensation schemes.
2Measurement precision
If DC level compensation is implemented, then the duty ratio accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent extracts and removes the harmful DC component from the differential input signal by using capacitors to block DC while passing AC signals. This extraction approach achieves DC level compensation without adding complex active compensation circuits. The capacitors selectively remove the DC portion of the signal, allowing the amplifier to operate with accurate duty ratio while maintaining relatively simple circuit structure.
Solution Approach 2:
The patent changes the coupling parameter from direct DC coupling to capacitive AC coupling. By modifying how the input signal is coupled to the amplifier (through capacitors rather than direct connections), the system achieves accurate duty ratio without requiring complex DC compensation mechanisms. This parameter change in the coupling method simultaneously improves duty ratio accuracy and maintains circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures the duty ratio of the output clock signal remains accurate even with varying DC levels of the differential input signal.
Implementation Method 1
a first capacitor; a second capacitor... the first capacitor and the second capacitor receives a differential input signal and form a first pair of signal paths
Data Source
AI summary
An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.