Clock Buffer Circuit for Low-Distortion Internal Clock Timing
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Solution Overview
Problem
Conventional clock buffer circuits in semiconductor memory devices suffer from duty distortion due to unequal time delays, leading to reduced accuracy and high-speed operation reliability, especially in high-speed DRAMs like QDR, where external noise and voltage variations cause tR/tF characteristics to differ, necessitating extensive correction by duty correction circuits.
Innovation Solution
A clock buffer circuit comprising a first clock buffer for normal-phase and a second clock buffer for reverse-phase signals, with an internal clock generator that generates rising and falling edges of the internal clock signal using the buffered versions of these signals, ensuring equal time delays and minimizing duty distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional clock buffer circuit is used, then the circuit structure is simple, but duty distortion occurs due to unequal time delays (tR/tF characteristics differ)
Solution Approach 1:
The clock buffer circuit is segmented into separate rising-edge buffer and falling-edge buffer paths. Each path independently controls the timing of its respective edge, allowing equalization of tR and tF delays through separate optimization without requiring complex interconnected correction circuits.
2Object-affected harmful factors
If external noise and voltage variations are present, then the clock buffer must handle environmental factors, but tR/tF characteristics become unequal causing duty distortion
Solution Approach 1:
The circuit performs preliminary equalization of rising and falling edge delays through dedicated buffer paths designed with matched characteristics. By pre-compensating for environmental variations in the buffer design itself, the circuit maintains reliable high-speed operation without requiring extensive post-processing correction.
3Manufacturing precision
If duty correction is extensively applied to correct tR/tF differences, then duty ratio accuracy improves, but the circuit complexity and correction requirements increase
Solution Approach 1:
The timing equalization function is extracted from a complex duty correction circuit and implemented directly in the clock buffer structure itself. By integrating the equalization capability into the buffer's core operation through separate rising/falling edge paths, the solution achieves accurate duty ratio without requiring additional external correction circuits.
Data Source
AI summary
A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.