Clock Buffer Edge Collection for Low Spur and Phase Noise
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Solution Overview
Problem
Conventional clock buffers experience high power consumption due to static current generated when NMOS and PMOS transistors are turned on for a long duration, leading to spur leakage and phase noise issues, and existing solutions either increase power consumption or degrade clock signal quality.
Innovation Solution
A clock buffer design incorporating high-pass filters and logical circuits to generate filtered input clock signals, which are used to control the turning on times of PMOS and NMOS transistors, avoiding simultaneous activation and utilizing edge collectors to combine falling and rising edges for output clock signals, thereby reducing static current and improving edge quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If NMOS and PMOS are designed larger for better noise performance, then noise performance is improved, but power consumption increases due to static current
Solution Approach 1:
The patent applies preliminary action by introducing a delay circuit that activates the PMOS transistor before the NMOS transistor turns off. This ensures that the PMOS is already conducting when the NMOS turns off, preventing the static current condition. The delay circuit uses a RC time constant (R1*C1) to create the appropriate timing sequence, allowing the transistors to switch without overlapping conduction periods while maintaining larger transistor sizes for noise performance.
2Use of energy by moving object
If delay circuit is introduced to control turn-on period of PMOS for lowering power consumption, then power consumption is reduced, but duty cycle of output clock signal is shortened and phase noise worsens
Solution Approach 1:
The delay circuit introduces a preliminary action by advancing the PMOS turn-on time relative to the NMOS turn-off time. The RC network (R1*C1) creates a delay that ensures the PMOS is already conducting before the NMOS turns off, eliminating static current without requiring excessive delay that would affect duty cycle. This preliminary timing adjustment reduces power consumption while maintaining proper clock signal characteristics.
3Object-affected harmful factors
If NMOS and PMOS are both turned on for long duration for better noise performance, then noise performance is improved, but static current increases causing spur
Solution Approach 1:
The delay circuit implements preliminary action by ensuring the PMOS transistor is activated before the NMOS transistor turns off. The RC time constant (R1*C1) creates a timing sequence where the PMOS is already in the conducting state when the NMOS turns off, preventing the simultaneous conduction that causes static current and spur. This allows the transistors to maintain larger sizes for noise performance without generating spur.
Data Source
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AI summary
The present invention provides a clock buffer (100) including a first circuit (110), a second circuit (120) and an edge collector (130), wherein the first circuit is arranged to receive an input clock signal (CK_in) to generate a first clock signal (CK1), the second circuit is arranged to receive the input clock signal to generate a second clock signal (CK2), and the edge collector is arranged to generate an output clock signal (CK_out) by using a falling edge of the first clock signal and a rising edge of the second clock signal.