Clock Buffer Edge Collector for Low Spur and Phase Noise
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Solution Overview
Problem
Conventional clock buffers experience high power consumption due to static current generated when NMOS and PMOS are turned on for a long duration, leading to spur leakage and phase noise issues in output clock signals.
Innovation Solution
A clock buffer design comprising a first and second circuit, along with an edge collector, where the first circuit generates a first clock signal and the second circuit generates a second clock signal, utilizing the falling edge of the first signal and the rising edge of the second signal to produce an output clock signal, while employing high-pass filters and logical circuits to avoid simultaneous turning on of PMOS and NMOS, thereby reducing static current and improving edge quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If NMOS and PMOS are designed larger for better noise performance, then noise performance is improved, but power consumption increases due to static current
Solution Approach 1:
The patent divides the clock buffer into two separate circuits: a first circuit that generates a first clock signal with good falling edge, and a second circuit that generates a second clock signal with good rising edge. Each circuit uses smaller transistors to reduce static current, while the edge collector combines the edges from both circuits to achieve low noise performance without the power penalty of oversized transistors in a single circuit.
2Use of energy by moving object
If delay circuit is added in front of PMOS to control turn-on period, then power consumption is reduced, but duty cycle is shortened and phase noise worsens
Solution Approach 1:
Instead of adding delay circuits to control PMOS turn-on, the patent segments the clock buffer into two independent circuits. Each circuit can be optimized with smaller transistors for reduced power consumption, while the edge collector combines their outputs to maintain proper duty cycle and minimize phase noise, avoiding the need for complex delay control circuits.
3Duration of action of moving object
If NMOS and PMOS are turned on for long duration, then clock signal transmission is maintained, but static current dominates power consumption and causes spur
Solution Approach 1:
The patent uses periodic action by generating two separate clock signals with complementary edge characteristics. The first circuit produces a signal with a good falling edge, while the second circuit produces a signal with a good rising edge. The edge collector combines these periodic signals to create an output clock signal that maintains proper transmission duration while minimizing static current and reducing spur through the alternating use of rising and falling edges from different circuits.
Data Source
AI summary
The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.