Clock Buffer Circuit Switching for Fast Low-Power Transitions
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Solution Overview
Problem
In low power applications, clock buffers face challenges in achieving fast transition times while minimizing power consumption, as slower transition times are often required to conserve power.
Innovation Solution
The proposed clock buffer circuit incorporates a feedback mechanism with transistors and switches that control the pull-up and pull-down networks, allowing them to operate in parallel or series. This configuration optimizes the time both networks are in the ON state, reducing short circuit current and power consumption while enhancing transition times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock buffer uses slow transition times to save power, then power consumption is reduced, but the ability to drive loads with improved transition times deteriorates
Solution Approach 1:
The patent applies dynamics by making the pull-up and pull-down networks configurable between series and parallel configurations. The feedback mechanism dynamically switches between these configurations based on the clock phase, allowing the transition time to be optimized for each phase while maintaining low power consumption during steady state operation
Solution Approach 2:
The patent changes the resistance parameter of the pull-up and pull-down networks by switching between series (higher resistance) and parallel (lower resistance) configurations. This allows the circuit to have low resistance during transitions for fast switching and high resistance during steady state for low power consumption
2Speed
If the clock buffer uses fast transition times to drive loads, then transition times are improved, but power consumption increases
Solution Approach 1:
The patent uses periodic action by applying the parallel configuration (fast transition) only during the brief transition periods of the clock signal, while using the series configuration (low power) during the steady high and low states. The feedback mechanism ensures the parallel configuration is activated only when needed for transitions
Solution Approach 2:
The dynamic switching between series and parallel configurations allows the circuit to have low resistance during transitions for fast switching and high resistance during steady state for low power consumption, resolving the contradiction between speed and energy use
3Speed
If the pull-up and pull-down networks operate in parallel to reduce resistance, then transition times are improved, but short circuit current increases
Solution Approach 1:
The patent uses feedback from the clock signal to control the switching of the pull-up and pull-down networks. The feedback mechanism ensures that the parallel configuration is activated only during appropriate transition phases, coordinating the operation of pull-up and pull-down networks to minimize overlap and reduce short circuit current while maintaining fast transition times
Data Source
AI summary
An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.