Computing Array Clock Buffer Delays for Dynamic IR Drop
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Solution Overview
Problem
Integrated circuits with accelerated processing functions experience excessive dynamic IR DROP due to simultaneous switching of a large number of transistors, causing voltage drops and affecting circuit safety and stability.
Innovation Solution
Incorporating clock buffers that delay and synchronize clock signals differently across computing array sub-circuits, preventing simultaneous transistor switching and reducing dynamic IR DROP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large-scale multiply-add circuit with many transistors is used for accelerated processing, then processing speed and computational capability are improved, but a very large current is generated in a short period when transistors switch simultaneously, causing excessive dynamic IR DROP and voltage instability
Solution Approach 1:
The clock signal distribution is segmented into multiple independent clock buffers, each serving different computing array sub-circuits. This segmentation allows transistors in different sub-circuits to switch at different times, distributing the current draw over time and reducing peak current and dynamic IR DROP while maintaining high processing speed capability
Solution Approach 2:
Different clock buffers introduce different delay durations to clock signals, creating periodic but non-synchronized switching patterns across computing array sub-circuits. This periodic action with varied phases ensures continuous high processing throughput while avoiding simultaneous transistor switching that causes excessive current spikes
2Stability of the object's composition
If clock signals are synchronized across all computing array sub-circuits, then processing coordination and data consistency are improved, but all transistors switch at the same time causing large current spikes and excessive dynamic IR DROP
Solution Approach 1:
The clock signal distribution system dynamically adjusts delay durations for different clock buffers, creating a dynamic, non-synchronized switching pattern. This dynamic approach maintains processing coordination through controlled timing relationships while avoiding the energy loss associated with simultaneous transistor switching across all sub-circuits
3Reliability
If multiple clock buffers with different delay durations are used to disperse transistor switching times, then dynamic IR DROP is reduced and circuit safety is improved, but device complexity increases
Solution Approach 1:
Multiple clock buffers perform the same basic function of clock signal distribution but with different configurable delay durations. This multi-functionality allows a single clock buffer design to serve multiple purposes by adjusting delay parameters, reducing the need for entirely different circuit designs and managing complexity through parameterization rather than structural diversity
Data Source
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AI summary
Embodiments of the present disclosure provide a computing array integrated circuit and a chip, wherein the computing array integrated circuit comprises: at least one clock buffer for delaying an input clock signal for a specified duration and outputting the delayed clock signal, the delayed clock signals output by different clock buffers not being synchronized; a plurality of computing array sub-circuits, each of the clock buffers being coupled to at least one computing array sub-circuit in the plurality of computing array sub-circuits, each of the computing array sub-circuits acquiring the delayed clock signal output by the respective corresponding clock buffer. Embodiments of the present disclosure may reduce the instantaneous dynamic power consumption pressure and improve the safety of the circuit.