Clock Buffer Current Control for Power-Supply Jitter Cancellation
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Solution Overview
Problem
Existing clock jitter suppression techniques fail to effectively reduce jitter at the clock supply destination circuit due to power supply noise, despite sufficient suppression at the clock generation circuit.
Innovation Solution
A jitter cancellation circuit comprising a clock buffer and a current control unit that adjusts the operating current of the clock buffer in an opposite phase to the fluctuation component of the power supply voltage, compensating for jitter caused by power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock propagation element (CTS or repeater) is used to transmit the clock, then the clock can be distributed to the supply destination circuit, but jitter is superimposed on the clock due to power supply noise
Solution Approach 1:
The patent measures the power supply voltage fluctuation (harmful factor) and uses it to control the clock buffer's operating current, converting the harmful power supply noise into a useful control signal that compensates for the jitter it causes
Solution Approach 2:
The patent implements a feedback mechanism where the power supply voltage fluctuation is measured and fed back to the current control unit, which adjusts the clock buffer's operating current to compensate for the jitter in real-time
2Speed
If the operating current of the clock buffer is increased to reduce delay time, then the delay time decreases, but the clock jitter suppression capability deteriorates
Solution Approach 1:
The patent dynamically adjusts the operating current of the clock buffer based on the measured power supply voltage fluctuation, allowing the system to optimize between speed and jitter suppression depending on the actual power supply conditions rather than using a fixed current
Data Source
AI summary
A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.