DC-Coupled Clock Buffer Switching for Fast Low-Power Level Shifting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DC-coupled clock buffers face challenges with high power consumption and reduced operating speed due to the serial combination of diode-connected and pull-down transistors, which limits their efficiency in level-shifting clock signals across different power domains.
Innovation Solution
A DC-coupled buffer design that incorporates a first pull-down NMOS transistor, a current mirror, and a switch transistor to control the discharge and charging of internal nodes, along with an inverter powered by a higher power supply voltage, to optimize the level-shifting process by minimizing power consumption and enhancing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DC-coupled buffer uses a serial combination of diode-connected transistor and pull-down transistor for level-shifting, then the buffer can operate without passive devices and without frequency restrictions, but the power consumption increases and operating speed decreases
Solution Approach 1:
The patent divides the single level-shifting stage into two separate stages: a first level-shifting stage with a pull-down transistor and current mirror, and a second level-shifting stage with another pull-down transistor. This segmentation eliminates the need for a diode-connected transistor in series, reducing continuous current discharge and lowering power consumption while maintaining DC-coupled operation across a wide frequency range
Solution Approach 2:
The patent employs clocked control signals to periodically enable and disable the pull-down transistors at appropriate times during the clock cycle. This periodic action ensures that both transistors are not simultaneously active, preventing continuous current discharge and reducing power consumption while maintaining the DC-coupled buffer's ability to operate without frequency restrictions
2Device complexity
If a DC-coupled buffer uses a serial combination of diode-connected transistor and pull-down transistor, then passive devices are eliminated, but the response speed is slowed due to current struggle between transistors
Solution Approach 1:
By separating the level-shifting function into two independent stages with separate pull-down transistors, the patent eliminates the current struggle that occurs in serial configurations. Each transistor operates independently in its own stage, allowing faster response times while maintaining the simplified DC-coupled structure without passive devices
Solution Approach 2:
The patent introduces an intermediate current mirror stage between the input and output pull-down transistors. This current mirror acts as a mediator that transfers the control signal from the first stage to the second stage without requiring the transistors to be in series, thereby eliminating the current struggle and improving response speed while maintaining the DC-coupled architecture
3Reliability
If current mirror transistor remains on during input clock signal rising edge, then level-shifting function is maintained, but the discharge of internal node is slowed
Solution Approach 1:
The patent uses clocked control signals to periodically enable the current mirror and pull-down transistors only during the falling edge of the input clock signal, and disables them during the rising edge. This periodic control maintains the level-shifting function when needed while eliminating the current struggle that would slow down the discharge during the rising edge, thereby improving response speed without sacrificing reliability
Data Source
AI summary
A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.