Clock Conditioning Buffer Using Two-Tap Filtering for Low-Jitter Interpolation
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Solution Overview
Problem
High-precision phase interpolators face challenges in generating low-jitter clock signals due to misalignment and errors caused by unsynchronized clock signals in modern high-speed applications, particularly in broadband communications and microprocessor circuitry, where clock waveforms often lack substantially overlapping edges, leading to high timing jitter.
Innovation Solution
A clock conditioning buffer circuit that utilizes a two-tap transversal filter with a fixed tap-to-tap delay, leveraging available quadrature clock phases to adjust the time constant and ensure overlapping edges, thereby reducing jitter and improving interpolation accuracy without requiring complex feedback systems or additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase interpolator is used to generate clock signals from unsynchronized inputs, then clock signal generation is achieved, but timing jitter increases due to misalignment and non-overlapping edges
Solution Approach 1:
The patent applies preliminary action by conditioning the input clock signals before they enter the phase interpolator. Specifically, the first and second clock signals are conditioned to have substantially overlapping edges in advance, ensuring that when interpolation occurs, the output clock signals maintain low jitter. This pre-conditioning of inputs resolves the timing jitter issue without requiring complex feedback mechanisms during operation.
2Manufacturing precision
If complex feedback systems are used to synchronize clock signals, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary approach by using a phase interpolator with conditioned input signals rather than complex feedback systems. The phase interpolator itself acts as a mediator that takes the conditioned clock signals and produces synchronized output signals with precise timing. This intermediary device achieves timing precision through its inherent interpolation capability combined with pre-conditioned inputs, avoiding the need for complex feedback control circuits.
3Manufacturing precision
If additional hardware is added to ensure overlapping clock edges, then jitter is reduced, but device complexity and hardware requirements increase
Solution Approach 1:
The patent applies self-service by designing the phase interpolator to work effectively with the available quadrature clock phases already present in the system. The interpolator utilizes these existing phases and conditions them internally to achieve overlapping edges, rather than requiring external hardware additions. This self-service approach reduces jitter while minimizing additional hardware requirements by leveraging existing system resources.
Data Source
AI summary
A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.