Clock Buffer Phase Compensation for PVT-Induced Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the operation speed of computer systems increases, existing clock signal distribution methods, such as the unmatched DQ-DQS scheme, face challenges in maintaining synchronization due to process, voltage, and temperature (PVT) variations, leading to jitter and insufficient setup and hold margins.
Innovation Solution
A clock generating circuit comprising a buffer circuit, a voltage control circuit, and a compensating circuit is introduced. The buffer circuit buffers the input clock signal, the voltage control circuit generates control voltages based on power voltage changes, and the compensating circuit adjusts the phase of the clock signal to maintain stability across varying PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of the computer system is increased, then the productivity is improved, but the clock signal becomes susceptible to jitter and delay time variation due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the actual delay time of the clock signal is measured and compared with the target delay time, and the PVT compensation amount is adjusted based on this comparison to maintain synchronized timing relationships. This closed-loop feedback ensures clock signal stability despite PVT variations during high-speed operation.
Solution Approach 2:
The patent dynamically adjusts the PVT compensation amount as a variable parameter to counteract the effects of process, voltage, and temperature variations. By changing this compensation parameter based on actual PVT conditions, the system maintains reliable clock signaling while operating at high speeds.
2Productivity
If the unmatched DQ-DQS scheme is used for high-speed operation, then the productivity is improved, but the setup and hold margins become insufficient due to PVT variations
Solution Approach 1:
The patent uses feedback to continuously monitor the timing relationship between clock and data signals, comparing actual delay with target delay, and adjusts the PVT compensation amount accordingly. This ensures that setup and hold margins are maintained even under high-speed unmatched DQ-DQS operation with PVT variations.
Solution Approach 2:
The patent introduces dynamic adjustment of the PVT compensation amount based on real-time PVT conditions and timing measurements. This dynamic adaptation allows the system to maintain precise timing synchronization despite the challenges of high-speed operation and environmental variations.
3Manufacturing precision
If the matched delay path is used to synchronize clock and data signals, then the timing synchronization is improved, but the device complexity increases
Solution Approach 1:
Instead of using complex matched delay paths, the patent achieves timing synchronization by dynamically adjusting the PVT compensation amount parameter. This parameter-based approach simplifies the circuit architecture while maintaining precise timing synchronization between clock and data signals.
Data Source
AI summary
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.