Multi-Phase Clock Buffer Phase Correction for Path Skew Control
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Solution Overview
Problem
Semiconductor circuits, particularly semiconductor memory devices, face performance degradation due to skews in multi-phase clock signals caused by differences in signal transmission paths, leading to data reliability issues.
Innovation Solution
A phase correction circuit that includes a test clock generation unit, a detection unit, and a control unit to detect and adjust phase skews in multi-phase clock signals by generating test clock signals and phase control signals, allowing these signals to pass through signal paths to correct delays and generate phase correction clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-phase clock signals are transmitted through different signal paths, then clock signals can be distributed to multiple destinations, but phase skews are introduced due to path differences
Solution Approach 1:
The patent generates test clock signals as copies of the original clock signal to measure phase skews in different signal paths. By creating identical test signals and routing them through various paths, the system can detect timing differences without affecting normal clock distribution
Solution Approach 2:
The detection unit measures phase skews and feeds this information back to the control unit, which then generates phase control signals to adjust delay elements. This closed-loop feedback mechanism continuously corrects phase skews to maintain data reliability
2Reliability
If phase correction is implemented using test clock signals, then phase skews can be detected and corrected, but the circuit complexity increases
Solution Approach 1:
The patent combines the test clock generation unit, detection unit, and control unit into an integrated phase correction circuit that works alongside the normal clock buffer. By merging these functions, the system achieves phase correction capability without requiring completely separate measurement and control systems
Solution Approach 2:
The patent introduces delay elements as intermediary components between the clock signal paths. These delay elements can be adjusted by phase control signals to compensate for phase skews, acting as mediators that fine-tune signal timing without fundamentally changing the signal paths
3Measurement precision
If delay adjustment is made to correct phase skews, then clock signal timing accuracy improves, but the response time for correction increases
Solution Approach 1:
The patent pre-configures multiple delay elements with different delay values before actual operation. When phase skews are detected, the control unit can immediately select and apply the appropriate pre-prepared delay adjustment, avoiding the need for real-time calculation and adjustment during critical timing windows
Data Source
AI summary
A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.