Clock Buffer Activation for Phase-Stable Low-Power Transitions
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Solution Overview
Problem
The change in phases of internal clock signals when semiconductor apparatuses transition between active and low power modes adversely affects their performance, leading to inconsistent operation.
Innovation Solution
A clock distribution network with a first and second global buffer, and a clock control circuit that manages enable signals to fully or partially activate these buffers based on operation modes, ensuring consistent performance while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal clock generation circuit is deactivated to reduce power consumption, then power consumption is reduced, but phase changes occur in the internal clock signals when the circuit is reactivated
Solution Approach 1:
The clock distribution network is divided into multiple independent global buffers (first global buffer, second global buffer, third global buffer) that can be selectively activated. This segmentation allows the circuit to maintain clock signal distribution capability while reducing power consumption by deactivating only the necessary portion of buffers during low power modes.
Solution Approach 2:
Instead of fully deactivating the clock generation circuit or all global buffers during low power modes, the patent applies partial action by selectively deactivating only the second and third global buffers while keeping the first global buffer active. This partial activation maintains sufficient clock signal distribution to prevent phase changes while reducing power consumption compared to full activation.
2Reliability
If all global buffers are fully activated to maintain clock signal stability, then phase stability is maintained, but power consumption increases
Solution Approach 1:
The clock distribution network implements dynamic buffer activation based on operation modes. The clock control circuit dynamically adjusts which global buffers are activated according to the current operational state (normal mode vs. low power mode), optimizing the balance between phase stability and power consumption in real-time.
Solution Approach 2:
The patent changes the activation state parameter of global buffers based on operation modes. In normal mode, more buffers are activated for optimal clock distribution, while in low power mode, fewer buffers are activated to reduce power consumption. This parameter change approach allows flexible adaptation to different operational requirements.
Data Source
AI summary
A clock distribution network includes at least two buffers that receive the same clock signal and generate different clock signals. In a first operation mode, the at least two buffers are all activated. In a second operation mode, one of the at least two buffers is activated. In the second operation mode, the other one of the at least two buffers is partially activated without being deactivated.