Clock Buffer Circuit for Instantaneous Video Pixel Clock Recovery
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Solution Overview
Problem
Existing video data receiver systems face latency and resource inefficiencies in recovering the pixel clock signal due to reliance on software interventions and phase-lock loops, especially during resolution changes and on-chip variations.
Innovation Solution
A circuit arrangement that generates a video pixel clock signal using a clock buffer circuit enabled by a single-bit video-clock-enable signal, eliminating the need for Mvid and Nvid values and phase-lock loops, and utilizing link symbol counts to mirror dynamic variations in the pixel data rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software intervention is used to recalculate pixel clock rate using Mvid and Nvid values, then pixel clock recovery accuracy is improved, but latency increases significantly
Solution Approach 1:
The patent replaces the software-based pixel clock recovery mechanism with a hardware-based circuit implementation. The circuit directly generates the pixel clock signal using a reference clock and a enable signal derived from link symbol extraction, eliminating the need for software calculations using Mvid and Nvid values. This hardware substitution reduces latency while maintaining clock recovery accuracy.
Solution Approach 2:
The patent creates a hardware circuit that replicates the pixel clock generation function previously performed by software. The circuit copies the essential functionality of calculating pixel clock rate from link symbol rates and timing parameters, but implements it in hardware logic to achieve instantaneous response without software iteration delays.
2Reliability
If phase-lock loop is used to recover pixel clock, then clock synchronization is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent extracts the essential clock generation function from the complex phase-lock loop system and implements it as a simplified hardware circuit. By taking out only the necessary functionality (generating pixel clock from reference clock with proper timing control) and removing the complex PLL feedback mechanisms, the patent achieves clock synchronization with reduced device complexity and resource requirements.
Solution Approach 2:
The patent replaces the expensive and resource-intensive phase-lock loop with a simpler, more economical hardware circuit implementation. The new circuit uses basic clock buffering and enable signal generation instead of complex PLL components, achieving the same synchronization function with fewer resources and lower complexity.
3Measurement precision
If Mvid and Nvid values are transmitted and processed, then pixel clock calculation accuracy is improved, but ease of operation deteriorates due to required software intervention
Solution Approach 1:
The patent replaces the software-based processing of Mvid and Nvid values with a hardware circuit that directly generates the pixel clock. The circuit uses the same underlying timing relationships but implements them in hardware logic, eliminating the need for software to read, interpret, and calculate clock rates from transmitted values. This maintains calculation accuracy while dramatically improving ease of operation.
4Adaptability or versatility
If multiple software iterations are required to recalculate pixel clock rate, then adaptability to dynamic changes is improved, but productivity decreases due to processing time
Solution Approach 1:
The patent replaces iterative software recalculation with a hardware circuit that responds instantaneously to changes in link symbol timing. The circuit continuously monitors the enable signal conditions and automatically adjusts the pixel clock generation in real-time, providing adaptability to dynamic changes without the processing delays inherent in multiple software iterations.
Solution Approach 2:
The patent implements continuous hardware-based clock generation that maintains uninterrupted pixel clock output. The circuit continuously processes timing information and adjusts clock generation in real-time, eliminating the stop-start nature of iterative software recalculation. This ensures continuous adaptability to dynamic changes while maintaining high productivity without processing interruptions.
Data Source
AI summary
A clock buffer has a clock-in port that inputs a reference clock and an enable port that inputs a video-clock-enable signal from a video receiver. The clock buffer generates a video pixel clock signal that has pulses of the reference signal as enabled by the video-clock-enable signal. The video receiver includes a link symbol extractor, a link-to-pixel mapper, and a timing generator that work to mirror the actual pixel data rate from the active period in a blanking period and thereby recover the actual video pixel clock.