Clock Buffer Power Reduction via PLL Mode Switching
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Solution Overview
Problem
Current DDR memory module topologies face challenges in managing clock scaling, leading to issues like additive jitter, clock skew, and margin constraints, especially at transfer rates above 5600 Mbps, which increases power consumption and reduces battery life in portable systems and increases thermal loads in enterprise systems.
Innovation Solution
The proposed solution involves a clock buffer device with a phase-locked loop (PLL) architecture that can switch between bypass mode and PLL modes based on the data transfer speed. In bypass mode, the PLLs are disabled to reduce power consumption when operating at speeds below 5600 Mbps, while in PLL modes (single-PLL or dual-PLL), the PLLs are engaged to manage clock signals effectively at higher speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLLs are enabled to manage clock signals at high speeds, then clock signal management quality is improved, but power consumption increases
Solution Approach 1:
The clock buffer device dynamically switches between bypass mode and PLL modes based on data transfer speed requirements. At speeds below 5600 Mbps, the device operates in bypass mode with PLLs disabled to minimize power consumption. When speeds exceed 5600 Mbps, the device transitions to single-PLL or dual-PLL modes to ensure proper clock signal management, thus adapting the power consumption level to the actual operational needs.
2Reliability
If dual-PLL mode is used for clock management, then clock signal quality at high speeds is improved, but device complexity increases
Solution Approach 1:
The clock buffer device is segmented into multiple operational modes (bypass mode, single-PLL mode, dual-PLL mode) that can be selectively activated. This segmentation allows the system to use only the necessary PLL infrastructure for each operating condition, reducing the effective complexity at any given time while maintaining the capability for high-performance clock management when needed.
3Speed
If clock scaling is increased to meet higher transfer rates, then data transfer speed is improved, but additive jitter and clock skew increase
Solution Approach 1:
The PLLs act as intermediary devices between the input clock signal and the memory interface. When activated in single-PLL or dual-PLL modes, they regenerate and condition the clock signals, thereby maintaining signal quality (reducing jitter and skew) even at higher data transfer rates where direct clock scaling would degrade performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption by up to 40 mW in bypass mode and achieves efficient clock signal management at higher speeds, thereby extending battery life and reducing thermal loads in information handling systems.
Implementation Method 1
a first phase-locked loop (PLL), and a second phase-locked loop (PLL)
Data Source
AI summary
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.