Local Clock Buffer Pulse Width Adjustment for Timing Violations
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Solution Overview
Problem
In electronic circuit design, existing methods struggle to efficiently address timing violations, particularly early and late mode violations, which can lead to increased silicon area usage and routability issues due to the need for delay cells and pads, and lack flexibility in balancing these violations.
Innovation Solution
A system and method that utilize a timing analysis engine and optimization tool to detect timing violations and determine whether to retain or modify the pulse width of local clock signals, allowing local clock buffers to generate clock signals with different pulse widths based on metrics associated with early and late mode violations, thereby optimizing the configuration of local clock buffers to reduce the need for delay cells and preserve chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If local clock buffers generate clock signals with fixed pulse width, then circuit design is simple, but timing violations cannot be optimized leading to increased silicon area usage
Solution Approach 1:
The patent applies dynamics by making the clock buffer configuration adjustable rather than fixed. The system dynamically selects between different pulse width configurations (first and second pulse widths) based on timing analysis results, allowing the clock buffer to adapt its behavior to different timing requirements and minimize silicon area usage.
Solution Approach 2:
The patent changes the pulse width parameter of the clock signal generated by local clock buffers. By analyzing timing violations and adjusting the pulse width parameter between two configured values, the system optimizes circuit performance and reduces the need for additional delay cells, thereby minimizing silicon area.
2Reliability
If delay cells are added to address timing violations, then timing constraints are met, but silicon area increases and routability becomes difficult
Solution Approach 1:
The patent performs preliminary timing analysis during the design phase to identify potential timing violations. By configuring local clock buffers with appropriate pulse widths before implementation, the system prevents timing violations from occurring, eliminating the need for additional delay cells and reducing silicon area.
Solution Approach 2:
The patent converts the potential harm of timing violations into a benefit by using the timing analysis information to optimize clock buffer configurations. Instead of adding delay cells to fix timing issues, the system uses the timing violation data to select appropriate pulse widths that prevent violations while minimizing area usage.
3Adaptability or versatility
If local clock buffers use single pulse width configuration, then device complexity is low, but flexibility in balancing early and late mode violations is limited
Solution Approach 1:
The patent applies local quality by providing different pulse width configurations to different local clock buffers based on their specific timing requirements. Each clock buffer can be independently configured with the most appropriate pulse width for its local timing constraints, optimizing performance without uniformly increasing complexity across the entire system.
Data Source
AI summary
Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.