Clock Buffer with Reference Enable Signal for DRAM Sequencing
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Solution Overview
Problem
Conventional semiconductor memory apparatuses, particularly DRAMs, face operational issues when the clock enable signal is enabled at specific timing points, leading to abnormal operation due to incorrect sequencing of internal clocks.
Innovation Solution
A clock buffer is designed with a reference enable signal generator and a delay enable signal generator to synchronize the output of internal clocks with the clock enable signal, ensuring correct sequencing and phase alignment, using a flip-flop configuration to maintain output levels regardless of input clock voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the clock enable signal is enabled when the second clock is at a high level, then the second clock is primarily output, but the semiconductor memory apparatus may abnormally operate
Solution Approach 1:
The patent applies preliminary action by generating a reference enable signal in advance through a delay circuit before the clock buffer operates. This reference enable signal is generated based on the clock enable signal and a reference clock, and is used to control the output sequence of internal clocks. By preparing the enable signal timing beforehand, the patent ensures that the first internal clock is always output before the second internal clock, preventing abnormal operation regardless of when the clock enable signal is activated.
2Use of energy by moving object
If the clock buffer transfers the delay clock to circuits in response to an enable signal, then power consumption is reduced, but the sequencing of internal clocks may become incorrect
Solution Approach 1:
The patent introduces a reference enable signal as an intermediary between the clock enable signal and the clock buffer operation. This reference enable signal is generated by a delay circuit that processes the clock enable signal along with a reference clock. The reference enable signal then controls the clock buffer to output internal clocks in the correct sequence. This intermediary mechanism ensures proper clock sequencing while allowing the clock buffer to remain inactive most of the time, thus maintaining low power consumption.
3Productivity
If the second clock is primarily output as the second internal clock, then the clock buffer operates, but the semiconductor memory apparatus may abnormally operate
Solution Approach 1:
The patent ensures that the reference enable signal is generated in advance through a delay circuit before the clock buffer operates. This preliminary generation of the enable signal controls the sequencing so that the first internal clock is always output before the second internal clock, preventing the abnormal operation scenario where the second clock would be primarily output.
4Speed
If the clock enable signal timing determines the primary clock output, then the system responds to enable signals, but the operation becomes unstable
Solution Approach 1:
The patent introduces a reference enable signal as an intermediary that decouples the direct relationship between clock enable signal timing and clock output sequencing. The reference enable signal is generated by a delay circuit that processes both the clock enable signal and a reference clock, ensuring that the first internal clock is always enabled before the second internal clock. This intermediary mechanism provides stable, predictable operation while maintaining fast response to enable signals.
Data Source
AI summary
A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock.