Clock Buffer Scan Gating to Cut Clock Grid Power Load
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Solution Overview
Problem
The high power consumption and inefficiency of clock networks in synchronous digital systems, particularly due to the need for multiple clocked devices and additional load on the clock grid for scan operations, hinder the development of low-power, high-performance circuits.
Innovation Solution
Implementing a local clock buffer that uses a non-clocked latch for the scan enable signal and derives the scan clock signal from the functional clock path, reducing the demand on the clock grid by eliminating clocked devices and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocked devices are used for scan operations, then scan functionality is achieved, but power consumption and load on clock grid increase
Solution Approach 1:
The patent combines the scan enable signal path with the functional clock path by using the same clocked latch (latch 310) to control both the functional clock gate (312) and the scan clock gate (370). This merging eliminates the need for separate clocked devices for scan operations, reducing power consumption and load on the clock grid while maintaining both functional and scan capabilities.
Solution Approach 2:
The single clocked latch (latch 310) serves multiple functions by controlling both functional and scan clock operations. The latch captures the scan enable signal and uses it to gate both functional and scan clock signals, making the clock buffer universally applicable to both operational modes without requiring additional clocked devices.
2Adaptability or versatility
If additional clocked devices are added for scan operations, then scan capability is provided, but device complexity increases
Solution Approach 1:
The patent merges the scan control functionality into the existing functional clock path by using the same clocked latch (latch 310) and clock buffer (300) to generate both functional and scan clock signals. This integration eliminates the need for additional clocked devices, reducing device complexity while maintaining full scan capability.
Solution Approach 2:
The clock buffer (300) and latch (310) are designed to serve both functional and scan operations universally. The same hardware components control both clock domains, reducing the overall number of devices required and simplifying the system architecture while providing both operational modes.
3Adaptability or versatility
If clock grid loads are increased for scan operations, then scan clock signals are provided, but energy efficiency decreases
Solution Approach 1:
The patent combines the scan clock signal generation with the functional clock signal path by using the same clock buffer (300) and deriving the scan clock signal from the functional clock path through the scan clock gate (370). This merging reduces the load on the clock grid by eliminating redundant clock distribution infrastructure, thereby improving energy efficiency while maintaining scan functionality.
Data Source
AI summary
A local clock buffer for improving energy efficiency using a power saving clock buffer for clock grid-based scanning includes a grid node that receives a global clock signal from a global clock grid; a clock enable latch configured to latch a clock enable signal, wherein the clock enable latch is clocked based on the global clock signal; a clock gate configured to output a functional clock signal in dependence upon a latched value of the clock enable signal; a scan clock enable latch configured to latch a scan enable signal, wherein the scan enable latch is a non-clocked latch; and a scan clock gate coupled to the output of the functional clock gate and configured to output a scan clock signal in dependence upon a latched value of the scan enable signal.