Clock Buffer Topology for Phase Skew Cancellation
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Solution Overview
Problem
Current clock distribution methods in coherent optical communication systems face challenges in accurately maintaining low skew between clocks, leading to time errors and voltage errors, especially at high speeds, and often require additional power and circuitry, which increases power consumption and sensitivity to device mismatch.
Innovation Solution
A skew-correcting clock buffer system using non-inverting push-pull source follower stages and CMOS inverters, where each output clock has equal contributions from two input clocks, allowing for cancellation of phase skew without increasing power consumption, and adjustable biasing circuits to introduce or remove skew as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock distribution methods are used, then clock signals can be distributed, but skew between clocks increases and measurement precision deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the skew detection circuit continuously monitors the skew between clock signals and feeds this information back to the skew correction circuit. This closed-loop feedback enables automatic adjustment and maintenance of low skew without requiring complex manual calibration or control systems.
Solution Approach 2:
The patent introduces intermediate circuits including a skew detection circuit that measures skew and a skew correction circuit that adjusts clock signals. These intermediary components act as mediators between the clock distribution network and the load, enabling precise skew control while keeping the overall system architecture relatively simple.
2Measurement precision
If additional circuitry is added to maintain low skew, then skew accuracy improves, but power consumption increases
Solution Approach 1:
The skew correction system operates autonomously by detecting skew conditions and automatically adjusting clock signals without requiring external control or additional power-intensive management circuits. The system serves itself by using the skew detection output directly to control the correction mechanism.
Solution Approach 2:
The skew correction circuit adjusts clock signal parameters (phase, timing) based on detected skew conditions rather than using additional power-intensive components. By dynamically changing signal parameters rather than adding substantial circuitry, the system maintains low power consumption while achieving high skew accuracy.
3Measurement precision
If additional circuitry is added to maintain low skew, then skew accuracy improves, but device complexity increases
Solution Approach 1:
The patent divides the clock distribution system into distinct functional segments: a skew detection circuit that measures skew, a skew correction circuit that adjusts signals, and the clock distribution network itself. This segmentation allows each component to be optimized independently and simplifies the overall design by assigning specific functions to separate modules.
Solution Approach 2:
The skew detection and correction circuits are designed to work with multiple clock signals and can be integrated into existing clock distribution architectures. The correction circuit can adjust various clock signals simultaneously, providing universal applicability across different parts of the system without requiring separate complex control mechanisms for each signal.
Data Source
AI summary
A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.