Current-Mode Clock Buffer Swing Detection for Lower Power
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Solution Overview
Problem
Conventional current-mode clock drivers are not power efficient, especially at high frequencies, due to increased power consumption in components like local oscillators and phase locked-loops, and struggle to control power consumption effectively in high-frequency clock interconnect circuits.
Innovation Solution
A current-mode driver circuit incorporating PMOS and NMOS transistors, variable conductivity circuits, and control circuits that adjust conductivity in response to voltage swings, utilizing biasing circuits with current mirrors and capacitors to optimize conductivity and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional current-mode clock drivers are designed to operate under worst case voltage, temperature and process conditions, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the conductivity of the variable conductivity circuits adjustable rather than fixed. The control circuit dynamically modifies the conductivity values based on actual operating conditions, allowing the system to adapt between worst-case and normal operating modes, thereby reducing power consumption while maintaining reliability when needed
Solution Approach 2:
The patent changes the conductivity parameter of the variable conductivity circuits based on detected voltage swing conditions. By adjusting conductivity dynamically rather than maintaining fixed worst-case values, the system reduces power consumption during normal operation while preserving reliability margins when needed
2Productivity
If the operating frequency of an IC increases, then productivity is improved, but power consumption of clock distribution circuit increases
Solution Approach 1:
The system dynamically adjusts the conductivity of variable conductivity circuits based on actual voltage swing detection, allowing high-frequency operation with reduced power consumption by avoiding fixed worst-case conductivity settings that would excessively increase power draw at high frequencies
3Reliability
If conventional current-mode buffers are designed for worst case conditions, then clock skew control is improved, but power efficiency deteriorates
Solution Approach 1:
The patent implements feedback by detecting the voltage swing at the output node and using this information to control the conductivity of the variable conductivity circuits. This closed-loop approach maintains clock skew control while optimizing power efficiency by adjusting conductivity based on actual operating conditions rather than assuming worst-case scenarios
Solution Approach 2:
The conductivity parameter is dynamically changed based on voltage swing detection, allowing the system to maintain adequate clock skew control while reducing power consumption by operating at optimized conductivity values rather than fixed worst-case values
Data Source
AI summary
A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.