Clock Receiver Buffer Isolation Across Voltage Domains

Solution Overview

Problem

Clock signals in data communication systems experience crosstalk and power supply-induced jitters due to capacitive coupling and variations in switching voltage thresholds, which can lead to performance degradation of Serializer-Deserializer (SerDes) circuits.

Innovation Solution

The implementation of a clock receiver circuit with buffer circuits operating in different voltage domains, using separate output voltages to isolate each buffer circuit and reduce crosstalk and power supply-induced jitters, allowing for the selection and output of clock signals at a clock output terminal in response to enable signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple buffer circuits are used to distribute clock signals to different voltage domains, then clock signal distribution capability is improved, but crosstalk and power supply-induced jitters increase due to capacitive coupling

Engineering Contradiction:

Improveclock signal distribution capabilityVSAvoidcrosstalk and power supply-induced jitters

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The clock receiver circuit is divided into multiple independent buffer circuits (first buffer circuit and second buffer circuit), each operating in a separate voltage domain with its own power supply voltage. This segmentation isolates the clock signals from different sources, preventing capacitive coupling and reducing crosstalk between them.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each buffer circuit is configured with different operating characteristics suited to its specific voltage domain. The first buffer circuit operates with a first power supply voltage while the second buffer circuit operates with a second power supply voltage, allowing each to be optimized for its local electrical environment and reducing interference.

Inventive Principle:

Principle #3Local quality

2Device complexity

If buffer circuits operate in the same voltage domain, then circuit design is simplified, but switching voltage threshold variations cause performance degradation

Engineering Contradiction:

Improvecircuit design complexityVSAvoidperformance stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Each buffer circuit is configured with different operating characteristics suited to its specific voltage domain. The first buffer circuit operates with a first power supply voltage while the second buffer circuit operates with a second power supply voltage, allowing each to be optimized for its local electrical environment and reducing interference.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the power supply voltage parameter for each buffer circuit to match its operating voltage domain. By adjusting this critical parameter, the buffer circuits operate at optimal switching thresholds for their respective domains, eliminating performance degradation caused by threshold variations.

Inventive Principle:

Principle #35Parameter changes

3Object-affected harmful factors

If separate power supply voltages are used for each buffer circuit, then crosstalk is reduced, but power consumption and circuit complexity increase

Engineering Contradiction:

Improvecrosstalk reductionVSAvoidpower domain management complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The clock receiver circuit is divided into multiple independent buffer circuits (first buffer circuit and second buffer circuit), each operating in a separate voltage domain with its own power supply voltage. This segmentation isolates the clock signals from different sources, preventing capacitive coupling and reducing crosstalk between them.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11334110B1Systems and methods for communicating clock signals

Publication Date: 2022.05.17 CADENCE DESIGN SYST INC

AI summary

In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.