Clock Bus Synchronization Circuit for High-Frequency Data Sampling
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Solution Overview
Problem
High-frequency master clock signals pose challenges in synchronizing data from multiple circuit blocks due to varying time delays, leading to potential data errors at high frequencies above 1 GHz.
Innovation Solution
A circuit and method involving a clock bus and synchronization unit that generates a third clock signal based on first and second clock signals from multiple circuit blocks, allowing for precise sampling of output data signals, thereby addressing the delay mismatch issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a master clock signal is used to directly clock the synchronization block, then the circuit complexity is reduced, but data synchronization accuracy deteriorates due to time delay differences between circuit blocks
Solution Approach 1:
The patent introduces a clock bus as an intermediary component that collects clock signals from multiple circuit blocks and generates a synchronized third clock signal. This mediator resolves the timing mismatch between different circuit blocks without requiring complex delay adjustment circuits, thus maintaining simplicity while improving synchronization accuracy.
Solution Approach 2:
The patent segments the clock signal generation function by having each circuit block generate its own clock signal based on the master clock, then combining these segmented clock signals on the clock bus to form a unified third clock signal for the synchronization block. This segmentation allows each block to operate independently while achieving collective synchronization.
2Productivity
If the master clock frequency is increased to increase throughput, then productivity is improved, but data synchronization reliability deteriorates due to difficulty in determining correct delay at high frequencies
Solution Approach 1:
The patent implements a dynamic clock synchronization mechanism where the third clock signal is continuously generated based on the actual timing of incoming data from multiple circuit blocks. This dynamic adaptation allows the system to maintain reliable synchronization even at high master clock frequencies up to 10 GHz, as the synchronization block adjusts its sampling timing according to actual data arrival times rather than relying on fixed delay calculations.
Solution Approach 2:
The clock bus implements a feedback mechanism where clock signals from various circuit blocks are fed back to generate the third clock signal. This feedback loop allows the synchronization block to automatically adjust its operation based on the actual timing characteristics of incoming data, ensuring reliable synchronization at high frequencies without requiring complex external delay adjustment circuits.
3Productivity
If different clock signals are provided to multiple circuit blocks to increase data processing capacity, then productivity is improved, but data synchronization accuracy deteriorates due to varying time delays
Solution Approach 1:
The patent creates a timing equipotential condition by having all circuit blocks reference the same master clock signal, ensuring they operate on a common timing baseline. The clock bus then equalizes any timing differences by generating a unified third clock signal that accounts for the varying delays of each block, allowing the synchronization block to sample all data with equal accuracy regardless of their different processing paths.
Data Source
AI summary
The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.