Pseudo-Differential Clock Calibration for Duty-Cycle Distortion
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Solution Overview
Problem
Duty-cycle distortion in pseudo-differential clocks limits the maximum operable frequency of sampled systems, particularly in sub-rate high-speed data communication links, due to inaccuracies in power supply and PVT variations, leading to ineffective duty-cycle calibration techniques.
Innovation Solution
A system with a differential sensing circuit and correction circuit using digital-to-analog converters (DACs) and current bleeder circuitry to adjust pseudo-differential clock signals, allowing for efficient duty-cycle calibration by comparing and inverting clock signals, thereby correcting duty-cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty-cycle calibration is performed using single-ended clock sensing with common-mode voltage reference, then the calibration can be implemented, but the calibration accuracy deteriorates due to PVT variations causing asymmetry in the clock signals
Solution Approach 1:
The patent applies asymmetry by using a differential sensing approach where one clock signal is intentionally inverted relative to the other. This creates a symmetric differential measurement system that compensates for PVT variations. The sensing circuit compares the non-inverted clock signal with its inverted counterpart, allowing the system to detect duty-cycle distortion while being immune to common-mode PVT variations that affect both signals equally.
Solution Approach 2:
The patent introduces a differential sensing circuit as an intermediary that compares the clock signal with its inverted version. This intermediary mechanism transforms the measurement problem from a single-ended comparison against a vulnerable common-mode reference to a differential comparison that inherently rejects PVT variations. The sensing circuit acts as a mediator that extracts duty-cycle information while eliminating the impact of power supply and environmental variations.
2Measurement precision
If duty-cycle calibration is performed sequentially on positive and negative polarity clocks using a shared detection circuit, then the calibration can be implemented, but the calibration time doubles
Solution Approach 1:
The patent merges the calibration of positive and negative polarity clocks into a single simultaneous operation. By using a differential sensing circuit that processes both clock signals together and a unified correction circuit that adjusts both signals concurrently, the system performs what would traditionally require two sequential calibration passes in a single integrated process. This combining of operations reduces calibration time while maintaining comprehensive calibration coverage for both polarities.
Solution Approach 2:
The correction circuit is designed with multi-functionality to handle both positive and negative polarity clock signals simultaneously. The same correction circuit infrastructure processes both clock polarities through differential control signals, eliminating the need for separate dedicated calibration circuits for each polarity. This universal approach enables parallel calibration of both signals, significantly reducing the overall calibration time while maintaining accuracy for both clock polarities.
3Ease of operation
If duty-cycle calibration uses level-shifting to accommodate positive potential power supply, then the calibration can be performed, but power supply inaccuracies cause calibration errors
Solution Approach 1:
The differential sensing circuit serves as an intermediary that compares the clock signal with its inverted version, creating a measurement system that is inherently immune to power supply variations. By using this differential comparison approach, the system eliminates the need for level-shifting operations that are vulnerable to power supply inaccuracies. The sensing circuit mediates the measurement process in a way that rejects common-mode power supply noise and variations, maintaining calibration accuracy without requiring additional level-shifting circuitry.
Solution Approach 2:
The patent implements a feedback mechanism where the differential sensing circuit continuously monitors the duty-cycle distortion and provides correction signals to the correction circuit. This closed-loop feedback system automatically compensates for duty-cycle variations caused by power supply inaccuracies and PVT variations. The feedback approach enables the system to maintain accurate calibration despite power supply fluctuations, eliminating the need for fragile level-shifting operations by using active compensation through feedback control.
Data Source
AI summary
A system includes a pseudo-differential clock path configured to convey a first clock signal and a second clock signal, wherein the second clock signal is inverted relative to the first clock signal. The system also includes a sensing circuit coupled to sensing nodes of the pseudo-differential clock path. The sensing circuit is configured to provide a sense signal based on a comparison of the first clock signal and the second clock signal at the sensing nodes. The system also includes a correction circuit coupled to the sensing circuit and to adjustment nodes of the pseudo-differential clock path. The correction circuit is configured to adjust the first clock signal and the second clock signal using digital-to-analog converters (DACs) and the sense signal.