Clock Duty Cycle Calibration Across Level Shifters Without Dividers
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect IC performance, particularly in level shifter circuits operating across different voltage domains, necessitating improved clock duty cycle management.
Innovation Solution
A clock duty cycle adjustment and calibration circuit comprising a ring oscillator, level shifters, a duty cycle adjustment circuit, and a duty cycle calibration circuit, which autonomously adjusts and calibrates clock duty cycles without analog voltage measurement, using a multiplexer and edge-triggered flip-flop to maintain consistent frequency and robustness against corrupted waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock duty cycle adjustment circuits are used, then frequency measurement and adjustment are possible, but the circuit complexity increases due to required frequency dividers and analog voltage measurement components
Solution Approach 1:
The patent extracts and eliminates the frequency divider component from traditional duty cycle measurement circuits. By using a rising edge detector and counter that directly process the input clock signal without requiring frequency division, the circuit achieves duty cycle measurement functionality with reduced complexity. The counter increments on rising edges and compares against a reference value to determine duty cycle, removing the need for separate frequency division stages.
Solution Approach 2:
The patent introduces a rising edge detector as an intermediary component that simplifies the measurement process. Instead of using complex frequency dividers and analog voltage measurement circuits, the rising edge detector generates clean trigger signals for the counter, enabling precise duty cycle measurement through digital counting. This intermediary digital signal processing approach replaces analog measurement paths and reduces overall circuit complexity.
2Measurement precision
If analog voltage measurement methods are used for duty cycle calibration, then calibration accuracy is achieved, but the circuit area increases and robustness against corrupted waveforms decreases
Solution Approach 1:
The patent replaces analog voltage measurement methods with a digital counting-based calibration system. The counter increments on each rising edge of the input clock signal and compares the count value against a reference value to determine duty cycle. This digital substitution eliminates the need for analog-to-digital converters, voltage dividers, and other analog measurement components, significantly reducing circuit area while maintaining calibration accuracy through precise digital counting and comparison.
Solution Approach 2:
The calibration circuit uses the input clock signal itself to perform calibration without requiring external analog measurement equipment. The rising edge detector and counter utilize the inherent timing information in the clock signal to self-calibrate the duty cycle measurement. This self-service approach eliminates complex external measurement paths and reduces circuit area by using the signal under test as the calibration reference.
3Measurement precision
If frequency dividers are included in the duty cycle adjustment circuit, then frequency measurement is accurate, but the device area and complexity increase
Solution Approach 1:
The patent extracts and removes the frequency divider component from the circuit architecture. Instead of dividing the input frequency to measure duty cycle, the design uses a counter that directly counts rising edges of the input clock signal within a fixed time period. This extraction of the frequency divider eliminates the need for multiple division stages and associated logic, reducing device area while maintaining measurement accuracy through direct edge counting.
4Manufacturing precision
If complex duty cycle adjustment circuits are used, then duty cycle control precision is improved, but the robustness against corrupted waveforms deteriorates
Solution Approach 1:
The patent inverts the traditional approach by using a rising edge detector that triggers on clean edge transitions rather than attempting to measure analog voltage levels that may be corrupted. By detecting the presence or absence of rising edges and counting them, the circuit achieves duty cycle control precision while being inherently robust to waveform corruptions such as noise, glitches, or amplitude variations. The digital edge detection method naturally filters out analog disturbances.
Data Source
AI summary
A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.