Clock Calibration Switching for Stable Multi-Node Synchronization
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Solution Overview
Problem
Terminal devices experience instability or crashes due to excessively large frequency deviations between clock nodes during clock calibration processes when they re-enter the coverage of an external reference timing signal.
Innovation Solution
Implement a clock calibration method that switches from using primary timing information to standby timing information when certain conditions are met, and adjusts timing information based on reference timing information to minimize frequency deviations, using a gradual adjustment process to ensure synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the terminal device performs level-by-level clock adjustment when re-entering external reference timing signal coverage, then the clock nodes can be synchronized with the reference signal, but the frequency deviation between clock nodes becomes excessively large causing instability or crashes
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the master clock node before lower-level clock nodes perform their adjustments. The master clock node is first calibrated to the reference timing signal, and only then do lower-level nodes adjust based on the master clock. This sequential pre-adjustment prevents excessive frequency deviations that would occur if all nodes adjusted simultaneously, thereby maintaining system stability while achieving synchronization.
2Productivity
If the terminal device adjusts all clock nodes simultaneously to match the reference timing signal, then synchronization is achieved faster, but the frequency deviation between nodes causes instability or crashes
Solution Approach 1:
The patent applies segmentation by dividing the clock calibration process into distinct hierarchical stages: first the master clock node adjusts to the reference signal, then intermediate clock nodes adjust to the master, and finally lower-level nodes adjust to their upper-level nodes. This segmented approach maintains system stability by preventing simultaneous adjustments while still achieving relatively fast calibration through parallel execution within each hierarchical level.
Data Source
AI summary
A clock calibration method and apparatus is provided, where the method includes a terminal device uses first timing information, adjusts second timing information of the terminal device based on reference timing information, and when determining that a first condition is met, switches from using the first timing information to using the second timing information. The first timing information is primary timing information, the second timing information is standby timing information, and the first condition includes that: the first timing information is different from the reference timing information, and the second timing information is the same as the reference timing information; or the first timing information is different from the second timing information; or the first timing information is different from the reference timing information.