Power-Density Clock Cell Spacing for Thermal Management
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Solution Overview
Problem
Densely packed clock cells in integrated circuits lead to local dynamic hot spots, increasing the likelihood of thermal runway and IR droop, while traditional spacing methods either fail to address these issues or sacrifice IC performance.
Innovation Solution
A method and system that determine keep-out regions for different types of clock cells based on their power-usage density, allowing for non-overlapping placement to reduce heat and IR droop while maintaining excellent timing closure and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock cells are densely packed to increase IC performance, then IC performance is improved, but local dynamic hot spots occur causing thermal runway and IR droop
Solution Approach 1:
The patent applies local quality by differentiating clock cell placement strategies based on local power density characteristics. Different keep-out region sizes are assigned to different clock cell types according to their specific power consumption profiles, allowing dense placement in low-power areas while maintaining spacing in high-power areas to prevent thermal runaway and IR droop.
2Object-affected harmful factors
If clock cells are spaced out to prevent thermal runaway and IR droop, then thermal issues are reduced, but IC performance is sacrificed due to timing-closure issues
Solution Approach 1:
The patent changes the parameter of clock cell spacing by introducing variable keep-out regions instead of fixed spacing. The keep-out region size is dynamically adjusted based on power density parameters of different clock cell types, enabling optimal balance between thermal management and timing closure for each specific cell type.
3Ease of manufacture
If a fixed spacing value is used for all clock cells to simplify placement, then placement is easier, but optimal spacing cannot be found for different power density clock cells
Solution Approach 1:
The patent segments the clock cell population into different types based on power density characteristics. Each segment (clock cell type) is assigned a specific keep-out region size, transforming the single uniform spacing problem into multiple targeted spacing requirements that can be automatically managed through cell type classification.
Data Source
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AI summary
Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.