Clock Signal Charge Sharing With Intermediate Voltage Precharge
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Solution Overview
Problem
In liquid crystal display (LCD) panels, the high peak-to-peak voltage difference in clock signals leads to significant power consumption due to parasitic capacitance, and existing charge-sharing schemes can cause delays in turning on gate lines.
Innovation Solution
A clock generation circuit with a charge storage component that transfers charge between two clock signals during different periods of the clock cycle, allowing for intermediate voltage levels between the high and low voltage states, reducing power consumption without direct charge sharing between the clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a charge-sharing scheme is used to reduce power consumption by parasitic capacitance, then power consumption is reduced, but delay in turning on gate lines occurs
Solution Approach 1:
The patent applies preliminary action by pre-charging the clock signal lines to an intermediate voltage level before the actual clock transition occurs. The charge storage component (capacitor) is pre-charged during the period when the clock signal is stable, so that when the clock transitions are needed, the charged capacitor immediately supplies charge to reduce the voltage swing. This preliminary charging action reduces the power consumption from parasitic capacitance without causing delay in gate line activation, because the charge is already available when needed.
2Stress or pressure
If voltage level shifter is used to boost clock signal voltage levels, then clock signal voltage levels are achieved, but power consumption by parasitic capacitance increases
Solution Approach 1:
The patent uses an intermediate voltage level as a mediator between the low voltage input clock signal and the high voltage output clock signal. Instead of directly boosting from low to high voltage (which causes large current spikes and high power consumption), the clock signal first transitions to an intermediate voltage level using a buffer, and then the charge storage component supplies additional charge to reach the final high voltage level. This intermediary approach reduces the instantaneous current demand and thereby reduces power consumption from parasitic capacitance.
Solution Approach 2:
The patent changes the voltage parameter by introducing an intermediate voltage level in the clock signal transition process. The clock signal voltage is divided into multiple stages: low voltage input → intermediate voltage (via buffer) → high voltage (via charge sharing). This parameter change strategy reduces the voltage swing magnitude at any single transition, which directly reduces the charge required to drive parasitic capacitance and thereby reduces power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by managing voltage levels efficiently and minimizing delays in gate line activation, optimizing the operation of LCD panels.
Implementation Method 1
A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low
Data Source
Figure 1~4a
Figure 2
Figure 3
AI summary
A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.