Clock Circuit Current Compensation for Synchronization Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Voltage converters experience an output voltage drop when clock signals generated by the clock circuit are synchronized with an external clock signal, leading to insufficient charging current for the capacitor, resulting in a missing clock signal.
Innovation Solution
A clock circuit with a current compensation circuit that generates a compensating current based on the frequency of the external clock signal to charge the capacitor, preventing output voltage drops by providing additional charging current when the clock signals are synchronized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock signal is synchronized with an external clock signal, then the clock circuit can operate in sync with external systems, but the charging current becomes insufficient causing voltage drop and potential clock signal loss
Solution Approach 1:
The current compensation circuit proactively detects the synchronization state and pre-adjusts the charging current before voltage drop occurs. When synchronization is detected, the circuit immediately compensates by increasing charging current to the capacitor, preventing the voltage drop that would otherwise cause clock signal loss.
Solution Approach 2:
The circuit continuously monitors the synchronization state between internal and external clock signals. Based on this feedback, the current compensation circuit dynamically adjusts the charging current magnitude, increasing it during synchronization periods when voltage drop risk is higher, and reducing it when operating independently.
2Device complexity
If discrete resistors are used to regulate clock signals, then the circuit design is simple, but the output voltage becomes unstable during clock signal transitions
Solution Approach 1:
The current compensation circuit acts as an intermediary between the clock signal generation and the capacitor charging process. It mediates the charging current to ensure sufficient current is always available, preventing voltage drops that would disrupt clock signal stability during transitions.
Solution Approach 2:
The circuit dynamically changes the charging current parameter based on operational mode. During external clock synchronization, the charging current is increased to compensate for higher power consumption and prevent voltage drop, while in independent mode the current returns to normal levels.
Data Source
AI summary
A clock circuit and control method thereof to avoid missing the clock signal generated by the clock circuit when the generated clock signal is synced with an external clock signal, wherein the clock circuit comprises a current compensation circuit and a current control circuit. The clock signal is generated by alternately charging and discharging a capacitor with a charging current based on a sync current and a compensating current when an external clock signal is detected. The compensating current is generated based on a frequency of the external clock signal, and the sync current is provided based on a phase difference between the generated clock signal by the clock circuit and the external clock signal.