Multi-Phase Clock Circuit with Dynamic Delay Selection
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Solution Overview
Problem
Existing digital logic circuits face issues with incorrect data registration due to fixed time delays in clock signal generation, which are affected by frequency changes and sensitive to PVT variations, leading to incorrect operation results and increased processor burden.
Innovation Solution
A multi-phase clock signal generating circuit with selectors to generate clock signals with specific time delays, allowing for flexible selection of clock signals with different phases and frequencies to trigger operation stages, reducing the burden on CAD processors and compensating for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit consisting of passive electronic devices (resistors and capacitors) is used to generate specific time delay, then the delay time is fixed, but the application is limited and incorrect registered data may be produced when clock signal frequency changes
Solution Approach 1:
The patent replaces fixed passive delay circuits with dynamic delay circuits that can adjust their delay time based on clock signal frequency. The delay circuit now actively responds to frequency changes, allowing the system to maintain accurate data registration across varying operating conditions by dynamically modifying the delay parameter.
Solution Approach 2:
The patent changes the delay parameter from a fixed value determined by passive components to a variable parameter that can be adjusted according to clock frequency. This allows the delay time to be modified in response to frequency changes, preventing incorrect data registration while maintaining system reliability across different operating frequencies.
2Device complexity
If fixed delay circuits are used, then the circuit design is simple, but the system is largely influenced by PVT (Process, Voltage, and Temperature) variations
Solution Approach 1:
The patent introduces feedback mechanisms that monitor PVT variations and adjust the delay circuit parameters accordingly. This feedback loop compensates for the influence of process, voltage, and temperature changes, maintaining stable operation and preventing synchronization issues without requiring overly complex circuit design.
3Ease of manufacture
If fixed delay circuits are used, then the initial design is straightforward, but the burden upon the processor increases in CAD applications
Solution Approach 1:
The patent implements self-service functionality where the delay circuit automatically adjusts its parameters based on detected operating conditions without requiring extensive processor intervention. This reduces the computational burden on the processor in CAD applications while maintaining design simplicity through automated adaptation.
Data Source
AI summary
A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.