Low-Pass Filtered Differential Clock Circuit for Duty-Cycle Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed electronic circuits face challenges in maintaining an accurate 50% duty cycle and 180° relative phase offset for clock signals due to limited bandwidth of PCB traces, leading to phase offsets caused by trace length mismatches.
Innovation Solution
A circuit employing self-referencing duty-cycle correction using serially-connected inverters, low-pass filters, and differential amplifiers to correct the duty cycle of received clock signals, ensuring accurate 50% duty cycle and 180° phase offset for internal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCB traces are used to distribute high-frequency clock signals, then clock signals can be delivered to circuits, but phase offsets and duty cycle errors occur due to trace length mismatches and limited bandwidth
Solution Approach 1:
The circuit uses a feedback mechanism where the output of the first inverter is fed back through a network of resistors and capacitors to the input of the first inverter. This feedback loop compensates for phase offsets and duty cycle errors by continuously adjusting the clock signal based on its own output characteristics, thereby resolving the phase accuracy issue caused by PCB trace limitations.
Solution Approach 2:
The circuit changes the electrical parameters of the clock signal by using a network of resistors (R1-R4) and capacitors (C1-C4) to adjust the signal characteristics. This parameter adjustment compensates for the phase offsets and duty cycle errors introduced by PCB trace length mismatches, transforming the degraded signal into an accurate clock signal.
2Speed
If PCB traces are used to distribute high-frequency clock signals, then clock signals can be delivered to circuits, but duty cycle accuracy deteriorates due to limited bandwidth
Solution Approach 1:
The feedback network formed by resistors R1-R4 and capacitors C1-C4 monitors the output duty cycle and adjusts the input signal characteristics accordingly. This closed-loop control maintains accurate 50% duty cycle despite the limited bandwidth of PCB traces by continuously compensating for signal degradation.
Solution Approach 2:
The circuit transforms the duty cycle parameter by using the RC network to reshape the clock signal waveform. The resistors and capacitors work together to restore the duty cycle to its intended value, compensating for the bandwidth limitations that would otherwise cause duty cycle errors.
3Adaptability or versatility
If trace length mismatches occur in PCB routing, then circuit layout flexibility is improved, but phase offset accuracy deteriorates
Solution Approach 1:
The feedback mechanism automatically compensates for phase offsets caused by trace length mismatches, allowing designers to use flexible PCB layouts without sacrificing phase accuracy. The feedback loop detects and corrects phase errors regardless of the physical trace lengths, enabling layout flexibility while maintaining precision.
Solution Approach 2:
The RC network acts as an intermediary between the PCB traces and the clock signal, mediating the effects of trace length mismatches. This intermediate circuit stage transforms the degraded signals from mismatched traces into accurate clock signals, allowing flexible routing while maintaining phase offset accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively corrects duty cycle and phase offset, enabling accurate clocking of ADCs and other circuits by averaging signals and applying corrections through differential amplifiers, thereby improving clock signal integrity.
Implementation Method 1
a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port
Implementation Method 2
a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters
Implementation Method 3
a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port
Data Source
AI summary
A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.