Clock Circuit Frequency Comparator for Mixed Signal Generation
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Solution Overview
Problem
Integrated circuits face damage and operational inefficiencies due to clock signals with frequencies that are too high or too low, leading to issues like program disturb, energy wastage, and voltage stress, as they often receive external clock signals that may exceed or fall below the designed maximum or minimum safe frequencies.
Innovation Solution
A frequency comparator is used to compare the external clock signal with an internal clock signal, allowing the integrated circuit to operate based on the internal clock if the external signal is too slow, thereby ensuring safe and efficient operation by generating a mixed clock signal within a predetermined frequency margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the integrated circuit operates with an external clock signal that is too slow (below minimum safe frequency), then the circuit can accept external clock signals with variable frequencies, but components may be damaged and program disturb may occur
Solution Approach 1:
The patent introduces an intermediary mechanism (frequency detection circuit and control logic) that mediates between the external clock signal source and the internal circuit components. This intermediary monitors the external clock frequency and selectively enables or disables operation based on whether the frequency falls within safe operating boundaries, thus protecting components while maintaining adaptability to external signals
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors the external clock signal frequency and adjusts its operational state accordingly. When the external clock frequency is detected to be below the minimum safe frequency, the feedback loop triggers a protective response (disabling operation or switching to internal clock), preventing damage while allowing normal operation when frequencies are appropriate
2Productivity
If the integrated circuit operates with an external clock signal that is too fast (above maximum safe frequency), then the circuit can process data faster, but components may be damaged and voltage stress increases
Solution Approach 1:
The frequency detection circuit acts as an intermediary that stands between the external clock source and the internal circuitry, monitoring the clock frequency and preventing harmful high-frequency signals from reaching sensitive components. This mediator enables the system to reject dangerous frequencies while accepting beneficial ones
Solution Approach 2:
The system performs preliminary detection of the external clock frequency before allowing operation to commence. By detecting potentially harmful high frequencies in advance and preventing operation under those conditions, the system avoids component damage and voltage stress before they can occur
3Use of energy by moving object
If the integrated circuit operates with a low-frequency clock signal, then energy consumption is reduced, but program disturb occurs and operation time increases
Solution Approach 1:
The feedback mechanism detects when the external clock frequency drops below the minimum safe threshold and triggers a protective response. This prevents the system from operating at dangerously low frequencies where program disturb would occur, while still allowing energy-efficient operation at appropriate low frequencies
Data Source
AI summary
Integrated circuits, apparatuses and methods are disclosed, such as a method that includes generating an internal clock signal, receiving an external clock signal, and providing a mixed clock signal at an output. The mixed clock signal has a frequency ranging from a defined maximum frequency of the external clock signal to a frequency margin below a frequency of the internal clock signal. Additional integrated circuits, apparatus and methods are described.