Clock Generation Circuit for Stable Communication During Frequency Switching
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Solution Overview
Problem
Existing clock generation techniques fail to maintain a constant communication clock signal frequency during transitions to low power consumption modes, leading to communication responsiveness issues when switching system clock frequencies.
Innovation Solution
A clock generation circuit with a system clock selection circuit, frequency division circuit, and communication clock selection circuit that synchronizes the communication clock signal with the system clock frequency switching, ensuring continuous communication by adjusting the division ratio of the frequency divider in response to selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the system clock frequency is reduced to enter low power consumption mode, then power consumption is reduced, but the communication clock signal frequency cannot be maintained constant
Solution Approach 1:
The patent divides the clock signal generation into separate functional blocks: a system clock selection circuit that selects between different frequency clocks, and a communication clock selection circuit that independently selects the appropriate divided clock signal. This segmentation allows independent control of system clock and communication clock, enabling the system to reduce power consumption while maintaining communication clock frequency stability.
Solution Approach 2:
The patent pre-generates multiple divided clock signals with different division ratios before the communication clock is needed. When transitioning to low power mode, the communication clock selection circuit can immediately switch to the pre-prepared divided clock signal with the appropriate frequency, avoiding delays and maintaining frequency stability without requiring real-time frequency detection or adjustment.
2Reliability
If the division ratio of the frequency divider is changed to adapt to system clock frequency switching, then the communication clock frequency can be maintained, but communication responsiveness deteriorates during the switching period
Solution Approach 1:
The patent pre-generates multiple divided clock signals with different division ratios (e.g., 1/2, 1/4, 1/8, 1/16) using separate frequency division circuits before they are needed. When the system clock frequency switches, the communication clock selection circuit can immediately select from these pre-prepared signals, eliminating the delay that would occur if the division ratio had to be changed in real-time. This ensures continuous communication without interruption.
Solution Approach 2:
The patent implements a dynamic selection mechanism where the communication clock selection circuit can switch between different divided clock signals based on the current system clock frequency. This dynamic switching capability allows the system to adapt to frequency changes while maintaining optimal communication performance, as the selection is based on predetermined division ratios rather than requiring real-time calculation or adjustment.
3Use of energy by stationary object
If the system clock frequency is switched during operation, then power consumption can be optimized, but communication disruptions occur during frequency transition
Solution Approach 1:
The patent pre-generates multiple divided clock signals corresponding to different system clock frequencies before switching occurs. When the system clock frequency transitions, the communication clock selection circuit immediately switches to the pre-prepared divided clock signal that corresponds to the new frequency, ensuring continuous communication without disruption. This eliminates the gap that would occur if the divided clock signal had to be generated in real-time after the frequency switch.
Solution Approach 2:
The patent introduces a communication clock selection circuit as an intermediary between the system clock selection circuit and the communication interface. This intermediary circuit receives multiple divided clock signals and selects the appropriate one based on the current system clock frequency, ensuring that the communication clock frequency is always appropriate even during system clock transitions. This mediator prevents communication disruptions by decoupling the communication clock from direct dependence on the system clock frequency changes.
Data Source
AI summary
A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal.