Temperature-Compensated Clock Circuit for Noise-Stable Timing
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Solution Overview
Problem
Existing clock circuits in integrated circuits are complex and costly due to their need to address variations in temperature, ground noise, and power noise, which affect the timing of the output clock signal, and there is a need for a more efficient approach to generate a uniform output clock signal.
Innovation Solution
The proposed solution involves a clock integrated circuit with a latch and timing circuitry that alternates between reference signals, using cross-coupled gates and inverter or Schmitt trigger circuitry to resist temperature variations, and incorporates a current generator-based reference circuit to generate temperature-compensated references, reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer circuits with active loads, independent bias circuitry, and bias circuitry are added to decouple power fluctuations from the clock signal, then the clock signal becomes more tolerant to power noise, but the device complexity and die area increase significantly
Solution Approach 1:
The patent extracts and eliminates the complex buffer circuits with active loads and independent bias circuitry from the clock circuit design. Instead of adding these components to decouple power fluctuations, the invention uses a simple inverter-based clock circuit that inherently tolerates power noise without requiring additional decoupling mechanisms, thereby reducing device complexity while maintaining reliability
Solution Approach 2:
The clock circuit is designed to be self-tolerant to power noise through the use of an inverter with a temperature-compensated trigger point. The circuit serves its own noise tolerance needs without requiring external buffer circuits or independent bias circuitry, eliminating the need for additional components while maintaining clock signal stability under power fluctuations
2Stability of the object's composition
If buffer circuits with active loads are used to isolate power fluctuations, then the clock signal stability improves, but the die area and manufacturing cost increase
Solution Approach 1:
The patent removes the buffer circuits with active loads that occupy significant die area. The invention achieves clock signal uniformity through a compact inverter-based design with temperature compensation, eliminating the need for large buffer circuits while maintaining signal stability
Solution Approach 2:
The invention replaces expensive, area-intensive buffer circuits with a simple, compact inverter design. The inverter with temperature-compensated trigger point provides the necessary clock signal uniformity at a fraction of the die area and manufacturing cost of traditional buffer circuit approaches
3Reliability
If complex buffer circuits are implemented to address temperature variations, then the clock signal becomes more temperature tolerant, but the device complexity increases
Solution Approach 1:
The patent changes the trigger point parameter of the inverter to be temperature compensated. By adjusting this electrical parameter rather than adding complex temperature compensation circuits, the clock signal becomes tolerant to temperature variations while keeping the overall circuit design simple and avoiding increased device complexity
Solution Approach 2:
The invention extracts and eliminates complex temperature compensation buffer circuits from the design. Instead, it uses a simple inverter with a temperature-compensated trigger point to achieve temperature tolerance, significantly reducing circuit complexity while maintaining reliability across temperature variations
Data Source
AI summary
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.