Semiconductor Clock Circuit for Multi-Oscillator Abnormality Detection
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Solution Overview
Problem
Existing semiconductor integrated circuits are unable to detect abnormal oscillations in both the ring oscillator output signal and the PLL output signal, as they lack the necessary mechanisms to monitor these signals independently, leading to potential operational failures.
Innovation Solution
Incorporating a selector and a determination circuit that switches between the clocks of multiple oscillators, allowing for counting up or down based on a third oscillator's clock to determine if any of the clocks exhibit abnormal oscillations, thereby enabling detection of abnormalities in the oscillator, PLL, and ring oscillator output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock monitor measures oscillator output signal using ring oscillator output signal as sampling clock, then abnormal oscillation detection is enabled, but the ring oscillator itself cannot be monitored for abnormalities
Solution Approach 1:
The monitoring function is segmented into multiple independent monitoring paths. Each oscillator (main oscillator, PLL oscillator, ring oscillator) has its own dedicated monitoring mechanism. The determination circuit is divided into multiple determination units, each responsible for monitoring specific oscillator signals independently, allowing comprehensive coverage without mutual interference.
Solution Approach 2:
Multiple monitoring functions are merged into a single integrated determination circuit. The circuit combines the monitoring of main oscillator output signal, PLL oscillator output signal, and ring oscillator output signal through unified counting and determination logic, achieving comprehensive monitoring while sharing common circuit resources.
2Measurement precision
If separate monitoring mechanisms are added for each oscillator, then detection accuracy improves, but device complexity and circuit scale increase
Solution Approach 1:
The determination circuit is designed with multi-functionality to perform multiple monitoring tasks using a single unified structure. The counting units and determination logic can process different oscillator signals (main oscillator, PLL oscillator, ring oscillator) through the same circuit framework, eliminating the need for separate dedicated monitoring circuits for each oscillator and thereby reducing overall device complexity.
Solution Approach 2:
Each oscillator signal monitors itself through the unified determination circuit. The circuit uses the oscillator's own output signal as the basis for monitoring, comparing it against expected frequency relationships without requiring external monitoring equipment, thus achieving accurate detection with minimal additional circuitry.
3Ease of operation
If the system monitors only oscillator output signal frequency, then detection is simple, but it cannot detect abnormalities in PLL output signal or ring oscillator output signal
Solution Approach 1:
The monitoring approach dynamically adapts to different oscillator types and signal characteristics. The determination circuit can switch between different monitoring modes depending on which oscillator is being monitored, adjusting the counting methodology and comparison criteria to match the specific frequency relationships of each oscillator type (main, PLL, or ring oscillator).
Solution Approach 2:
The system implements feedback mechanisms where the determined abnormality results are fed back to verify the monitoring effectiveness. The determination units continuously compare actual oscillator signals against expected behavior, and when abnormalities are detected in any oscillator (main, PLL, or ring), the system generates appropriate abnormality determination signals that provide feedback on the monitoring system's own performance.
Data Source
AI summary
A semiconductor device includes a first oscillator that generates a first clock signal, a second oscillator that generates a second clock signal in response to the first clock signal, a third oscillator that generates a third clock signal, a counter that counts a signal corresponding to the first clock signal or a signal corresponding to the second clock signal during a predetermined period that is set based on the third clock signal to generate an overflow signal indicating that a count value of the signal corresponding to the first clock signal or the signal corresponding to the second clock signal exceeds a predetermined value, and an abnormality notice unit that receives the overflow signal to generate an abnormal signal indicating that an abnormal oscillation occurs in at least one of the first to third clock signals.