Clock Circuit Placement in Integrated Circuits
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Solution Overview
Problem
Existing methods for placing clock circuits in integrated circuits, such as simulated annealing, face challenges like long run times, failure to converge to optimal solutions, and variability in results, making debugging difficult and inefficient.
Innovation Solution
A method using a branch and bound placement algorithm that determines the order of clock circuits based on resource requirements and locks components to specific sites, optimizing the placement of clock circuits in integrated circuits by selecting appropriate locations and ensuring placement restrictions are met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simulated annealing is used for placing clock circuits, then the placement can be performed with simple implementation, but the run time becomes excessively long and convergence is not guaranteed
Solution Approach 1:
The patent applies preliminary action by pre-ordering clock circuits based on their resource requirements before performing placement. This ordering step is executed beforehand to guide the subsequent placement process, allowing the algorithm to make informed decisions about which clock circuits to place first, thereby reducing overall placement time while maintaining implementation feasibility.
Solution Approach 2:
The patent changes the parameter of placement ordering from random (as in simulated annealing) to a deterministic order based on resource requirements. By sorting clock circuits according to their resource needs, the algorithm transforms the placement process into a more efficient sequence, improving productivity without significantly increasing implementation complexity.
2Ease of manufacture
If simulated annealing with random swaps is used, then the placement process can be simplified, but the results become variable and debugging becomes difficult
Solution Approach 1:
The patent pre-orders clock circuits based on resource requirements before placement, creating a deterministic sequence. This preliminary ordering ensures that the same input always produces the same placement sequence, guaranteeing result consistency and making debugging straightforward, while the overall process remains relatively simple.
Solution Approach 2:
Instead of using random swaps as in simulated annealing, the patent inverts the approach by using a deterministic ordering based on resource requirements. This inversion from random to deterministic ordering eliminates result variability while maintaining process simplicity.
3Productivity
If clock circuits are placed without considering resource requirements, then the placement process is faster, but placement restrictions are more likely to be violated
Solution Approach 1:
The patent changes the ordering parameter from arbitrary or random to resource-based ordering. By sorting clock circuits according to their resource requirements, the algorithm ensures that circuits with stricter resource needs are placed first, guaranteeing compliance with placement restrictions while maintaining efficient placement speed.
Solution Approach 2:
The patent performs preliminary ordering of clock circuits based on resource requirements before the actual placement. This pre-processing step ensures that placement restrictions are considered from the outset, preventing violations while keeping the main placement process fast and efficient.
Data Source
AI summary
A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.