Single-Path Clock Circuit for PVT-Resilient Low-Voltage Operation
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, they face challenges with operating voltages decreasing, affecting performance due to susceptibility to process, voltage, and temperature (PVT) variations, as well as clock slew variations, which impact the reliability and range of operating voltages of clock circuits.
Innovation Solution
The implementation of a clock circuit design that uses a single clock trigger circuit to control both the latch and trigger circuits, providing a single clock enable path, which enhances immunity to PVT variations and clock slew variations, and incorporates a level shifter circuit for dual-rail memory designs to expand the range of operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock circuit designs are used, then the circuit structure is simple, but the immunity to PVT variations and clock slew variations is poor
Solution Approach 1:
The patent combines the latch circuit and trigger circuit into a unified structure where a single clock trigger circuit controls both components. This merging eliminates multiple independent clock enable paths, thereby improving immunity to PVT and clock slew variations while maintaining manageable circuit complexity through integrated design.
Solution Approach 2:
The clock trigger circuit is designed to serve multiple functions: it controls both the latch circuit and the trigger circuit, and generates clock enable signals for both. This multi-functionality reduces the number of separate control paths, improving reliability against PVT variations without proportionally increasing overall circuit complexity.
2Volume of moving object
If operating voltage is decreased to scale down IC size, then device miniaturization is achieved, but performance deteriorates due to increased susceptibility to PVT variations
Solution Approach 1:
By merging the control paths of the latch and trigger circuits under a single clock trigger circuit, the patent reduces the number of vulnerable interfaces and control signals. This integration makes the circuit more robust to PVT variations, enabling reliable operation at lower voltages required for IC miniaturization.
3Adaptability or versatility
If multiple clock enable paths are used, then flexibility is increased, but susceptibility to clock slew variations increases
Solution Approach 1:
The patent merges multiple clock enable paths into a single unified path controlled by one clock trigger circuit. This eliminates the susceptibility to clock slew variations that arises from multiple independent paths while maintaining the necessary flexibility through the circuit's ability to enable both latch and trigger functions through the same control mechanism.
Data Source
AI summary
A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.