Clock Circuit for Strobeless Memory Using RC Filter Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer environments with shared memory access, generating an accurate clock signal for data retrieval from memory devices that do not generate a strobe is challenging due to delays and variations in flight time and access time, leading to potential errors.
Innovation Solution
A clock circuit for a memory controller that uses a processor clock signal to generate both input and feedback clock signals, utilizing a driver in series with a resistor and an RC filter, where the input to the RC filter is tapped between the driver and resistor, facilitating a single line for clocking and improving synchronization during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the processor clock signal is used directly for memory access, then the clock signal generation is simple, but the accuracy deteriorates due to delays in flight time and access time
Solution Approach 1:
The patent introduces an RC filter as an intermediary component between the processor clock signal and the memory access operations. This RC filter generates a delayed clock signal that compensates for the flight time and access time delays, thereby maintaining clock signal accuracy without requiring complex timing circuits. The intermediary RC circuit absorbs the timing discrepancies while keeping the overall system relatively simple.
2Measurement precision
If a strobe is generated from memory, then the clocking accuracy is improved, but the device complexity increases
Solution Approach 1:
Instead of generating the clock signal from the memory device (as in traditional strobe-based systems), the patent inverts the approach by generating the clock signal from the processor side using an RC filter. This inversion eliminates the need for the memory device to generate a strobe, thereby reducing memory device complexity while still achieving accurate clocking through the processor-generated delayed clock signal.
3Measurement precision
If re-clocking is performed to account for delays, then the clocking accuracy is improved, but the difficulty of implementation increases due to variations in flight time and external factors
Solution Approach 1:
The patent changes the parameter of clock signal generation from direct processor clock to RC-filtered delayed clock. By modifying the clock signal parameters through the RC filter's time constant, the system automatically compensates for variations in flight time and access time. This parameter-based approach is simpler than active re-clocking mechanisms and is less sensitive to external variations such as temperature, as the RC filter's delay characteristics remain relatively stable.
Data Source
AI summary
This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.