Clock-Coded Pulse Recovery Circuit for High-Speed Synchronization
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in synchronizing internal circuits with high-speed operations, requiring effective signal recovery mechanisms to maintain clock synchronization and ensure accurate signal transmission.
Innovation Solution
A signal recovery circuit comprising a clock code generation circuit and a pulse recovery circuit, which generate codes and output pulses corresponding to a predetermined clock cycle, enabling synchronized operations by determining the enable period of output pulses based on input pulses and code values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor integrated circuits operate at high speed, then productivity is improved, but signal synchronization reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the recovery circuit monitors incoming signals and adjusts pulse generation accordingly. The circuit uses the phase and frequency information of received signals to control the timing and duration of output pulses, ensuring synchronization is maintained even at high operating speeds.
Solution Approach 2:
The patent introduces a recovery circuit as an intermediary component between the signal source and internal circuits. This intermediary circuit generates standardized output pulses based on received signals, acting as a buffer that ensures proper synchronization without requiring direct coupling between high-speed signal sources and internal circuitry.
2Measurement precision
If signal transmission accuracy is improved, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the signal recovery function into distinct operational phases: signal reception, pulse generation, and pulse output. By segmenting the recovery circuit into separate functional blocks, each handling a specific aspect of signal processing, the design achieves high transmission accuracy while keeping individual circuit blocks relatively simple and manageable.
Data Source
AI summary
A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.