Clock Compensating Circuit for PVT-Stable Memory Data Strobes

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Solution Overview

Problem

Memory devices, such as DRAM, face data transmission failures or delays due to process, voltage, and temperature (PVT) variations affecting the clock signal, leading to issues with data strobe signal duty ratio changes and pulse failures.

Innovation Solution

A compensating circuit comprising switching and pulse adjusting circuits that adjust voltage levels based on clock signals, feeding back voltages to maintain target levels and prevent duty ratio changes or pulse failures, ensuring reliable data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock pulse signal is generated based on the inner clock, then the memory device can transmit data to the memory controller, but PVT variation causes the clock pulse signal to fail or be delayed

Engineering Contradiction:

Improvedata transmission reliabilityVSAvoidPVT variation effect

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements feedback mechanisms where the first and second pulse adjusting circuits monitor the voltage levels of their respective output nodes and adjust the clock signal accordingly. The circuits feed back voltage information to maintain stable operation despite PVT variations, ensuring reliable data transmission.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the voltage level parameter of the clock signal dynamically. The first pulse adjusting circuit adjusts the voltage level of the first output node, and the second pulse adjusting circuit adjusts the voltage level of the second output node, to compensate for PVT variations and maintain reliable data transmission.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If switching circuits are used to control pulse adjustment, then voltage levels can be adjusted dynamically, but the circuit complexity increases

Engineering Contradiction:

Improvevoltage adjustment capabilityVSAvoidcircuit structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the clock signal processing into two separate paths with independent switching circuits and pulse adjusting circuits. The first path handles the first clock signal with its own switching and adjustment components, while the second path handles the second clock signal independently. This segmentation allows dynamic voltage adjustment while maintaining manageable circuit complexity through modular design.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11189333B2Compensating circuit for compensating clock signal and memory device including the same

Publication Date: 2021.11.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.