Clock Compensation Circuit for Phase Error Control
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Solution Overview
Problem
High-speed data processing in semiconductor memory devices is hindered by phase errors in multi-phase clock signals, which degrade operation speed and performance.
Innovation Solution
A clock compensation circuit that includes a delay circuit, voltage conversion circuit, comparison circuit, and phase error control circuit to generate and adjust clock signals, convert phase differences into voltages, and monitor phase errors to compensate for phase differences between multi-phase clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of clock signals is increased to achieve high-speed data processing, then productivity is improved, but phase errors between multi-phase clock signals occur causing reliability to deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where phase difference detection signals are generated by comparing phase difference voltages with a reference voltage, and these detection signals are fed back to control the delay amounts of delay circuits. This closed-loop feedback system continuously monitors and corrects phase errors, enabling the system to maintain reliable phase alignment even at high clock frequencies
Solution Approach 2:
The patent dynamically adjusts the delay parameter of delay circuits based on detected phase errors. By changing the delay amount parameter in response to phase difference detection signals, the system compensates for phase errors and maintains accurate phase relationships between multi-phase clock signals at high frequencies
2Reliability
If delay circuits are added to compensate phase errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs voltage conversion circuits that perform multiple functions: they convert phase differences between clock signals into voltage signals, and simultaneously generate phase difference detection signals by comparing with reference voltage. This multi-functional design reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while maintaining reliability
3Measurement precision
If phase difference detection and compensation circuits are implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the voltage conversion function and phase difference detection function into an integrated comparison circuit. The circuit compares phase difference voltages with reference voltage to generate detection signals, merging multiple measurement and control functions into a single circuit block. This reduces the number of separate components and simplifies the overall device structure while maintaining high measurement precision
Data Source
AI summary
A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.