Clock Cone State Restoration for Coherent Hardware Emulation
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Solution Overview
Problem
Conventional hardware emulation systems are inefficient due to serial evaluation of clocks and data inputs, which slows down emulation speed and causes inefficiencies by requiring clocks to fully propagate before evaluating sequential elements.
Innovation Solution
The evaluation of derived clocks and flip-flops/latches is performed in parallel, with the clock cone reverted to its previous state at breakpoints to provide a coherent view of the design, allowing for direct comparison with other emulators or hardware, and enabling observability and controllability during emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clocks and data inputs are evaluated serially in conventional hardware emulation systems, then the emulation process maintains simplicity and ease of operation, but the emulation speed and productivity are significantly reduced
Solution Approach 1:
The patent applies preliminary action by evaluating clock signals before data inputs in a controlled sequence. The system pre-evaluates clock cone changes and stores them, then uses this pre-computed clock information to evaluate sequential elements. This preliminary clock evaluation enables the system to achieve parallel processing benefits while maintaining manageable complexity through structured pre-computation and storage of clock states.
2Productivity
If clock and data evaluation are performed in parallel to improve emulation performance, then productivity increases, but the design state coherence and ease of operation deteriorate due to counterintuitive states at breakpoints
Solution Approach 1:
The patent applies copying by creating and storing copies of clock cone states at specific evaluation points. When a breakpoint is encountered, the system retrieves the previously stored clock cone state copy and restores it, ensuring that the displayed design state corresponds to the expected logical reference cycle. This copying mechanism allows parallel evaluation to proceed while maintaining coherent and intuitive design states for user observation and control.
Solution Approach 2:
The system implements feedback by monitoring evaluation progress and detecting breakpoints during parallel clock and data evaluation. When a breakpoint is detected, the system provides feedback to restore the clock cone to its previous state, ensuring coherence between the emulated design state and the user's expectations. This feedback mechanism maintains ease of operation by keeping the design state intuitive even during high-performance parallel evaluation.
3Ease of operation
If the entire design is presented in the same phase to maintain coherence, then ease of operation improves, but the emulation performance and productivity are reduced
Solution Approach 1:
The patent applies segmentation by dividing the emulation process into distinct phases: clock cone evaluation, data input evaluation, and state restoration. The system segments the evaluation of clocks and data into separate parallel processes, then uses checkpointing and state restoration to maintain coherence. This segmentation enables high-performance parallel evaluation while ensuring that the final presented state is coherent and intuitive for users, thus achieving both productivity and ease of operation.
Data Source
AI summary
The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed. Moreover, during cycle K+1 of the emulation, the values of the sequential elements are computed based cycle K values of the clocks. When the emulation is halted due to a break, the clock cone is reverted to its previous state. This Abstract is not intended to limit the scope of the claims.