Multi-Phase Clock Configuration Circuit for IC Pin Reduction
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Solution Overview
Problem
Integrated circuits (ICs) require a large number of pins for configuration, leading to increased volume, as the number of operational modes increases, necessitating a reduction in pin count for initialization.
Innovation Solution
A configured circuit and method utilizing a decision circuit to detect phase differences between reference and input clock signals, generating configuration data, and a multiple-phase clock generating circuit to share terminals for both configuration and operation modes, reducing the need for multiple pins through a switch module or multiplexer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of operational modes of IC is increased, then the functionality and versatility of IC is improved, but the number of pins required for configuration is increased
Solution Approach 1:
The patent applies multi-functionality by enabling pins to serve dual purposes: during initialization, pins receive configuration voltages to set operational modes, and during normal operation, the same pins transmit data signals. This is achieved through control circuits that manage the timing and state of pins, allowing them to be reused for different functions at different times, thereby reducing the total number of pins needed while supporting multiple operational modes.
Solution Approach 2:
The patent merges the configuration function and data transmission function into the same physical pins. By combining these previously separate functions into a single set of pins, the invention reduces pin count while maintaining the ability to support multiple operational modes through temporal separation of functions.
2Adaptability or versatility
If the number of pins of IC is increased, then the configuration capability for multiple operational modes is improved, but the volume of IC is increased
Solution Approach 1:
The patent applies multi-functionality by enabling pins to serve dual purposes: during initialization, pins receive configuration voltages to set operational modes, and during normal operation, the same pins transmit data signals. This is achieved through control circuits that manage the timing and state of pins, allowing them to be reused for different functions at different times, thereby reducing the total number of pins needed while supporting multiple operational modes.
Solution Approach 2:
The patent merges the configuration function and data transmission function into the same physical pins. By combining these previously separate functions into a single set of pins, the invention reduces pin count while maintaining the ability to support multiple operational modes through temporal separation of functions.
3Ease of operation
If separate terminals are used for configuration and operation modes, then the ease of configuration is improved, but the pin count is increased
Solution Approach 1:
The patent applies dynamics by making the pin functionality changeable over time. Pins dynamically switch between configuration mode (receiving voltage inputs during initialization) and operation mode (transmitting data signals during normal function). This temporal dynamic behavior allows the same pins to serve different purposes at different times, reducing pin count while maintaining ease of configuration through controlled state transitions.
Solution Approach 2:
The patent applies multi-functionality by enabling pins to serve dual purposes: during initialization, pins receive configuration voltages to set operational modes, and during normal operation, the same pins transmit data signals. This is achieved through control circuits that manage the timing and state of pins, allowing them to be reused for different functions at different times, thereby reducing the total number of pins needed while supporting multiple operational modes.
Data Source
AI summary
A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a phase difference between the input signal and the reference signal and outputs a configuration data according to the phase difference between the input signal and the reference signal.


