Clock Control Circuit Adjusts Local Clock for Audio Sync
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Solution Overview
Problem
Frequency deviation between crystal oscillators in source and sink devices leads to unsynchronized audio playback, with conventional solutions like resampling causing overcorrection, power consumption, and latency.
Innovation Solution
An electronic device with a receiver circuit, clock generator circuit, and clock control circuit that adjusts its local clock based on clock information from another device, allowing for semi-synchronization without the need for resampling, thereby reducing frequency deviation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resampling is implemented to correct frequency deviation, then audio playback synchronization is improved, but power consumption increases and latency is introduced
Solution Approach 1:
The patent extracts and removes the resampling function from the audio processing chain. Instead of using hardware or software resamplers to correct frequency deviation, the system directly uses the crystal oscillator output at the target sampling rate, eliminating the need for resampling operations and thereby reducing power consumption and latency while maintaining audio playback synchronization.
Solution Approach 2:
The patent segments the frequency deviation compensation function from the audio processing path. By separating the clock generation function (handled by the crystal oscillator) from the audio processing function, the system achieves frequency accuracy without requiring resampling operations, thus resolving the contradiction between synchronization reliability and power consumption.
2Reliability
If hardware-based SRC is used to correct frequency deviation, then audio playback synchronization is improved, but latency increases by about 1.54 ms
Solution Approach 1:
The patent removes the hardware SRC block from the audio processing chain and replaces it with a direct connection from the crystal oscillator to the audio processing modules. This extraction eliminates the processing delay introduced by hardware resampling, reducing audio latency by approximately 1.54 ms while maintaining synchronization accuracy through the use of a precision crystal oscillator.
3Reliability
If software-based SRC is implemented to correct frequency deviation, then audio playback synchronization is improved, but processing complexity and power consumption increase
Solution Approach 1:
The patent extracts the frequency correction function from the software processing domain and implements it at the hardware clock generation level using a precision crystal oscillator. This eliminates the need for software-based resampling algorithms, reducing processing complexity and power consumption while maintaining audio playback synchronization through accurate clock generation.
4Reliability
If resampling is used to correct frequency deviation, then clock synchronization is improved, but additional components and processing stages are required
Solution Approach 1:
The patent removes the resampling stages (both hardware and software) from the audio processing chain and replaces them with a direct crystal oscillator output. This extraction simplifies the system architecture by eliminating additional components and processing stages, achieving clock synchronization through the inherent accuracy of the crystal oscillator rather than through complex resampling operations.
Data Source
AI summary
An electronic device includes a receiver circuit, a clock generator circuit, and a clock control circuit. The receiver circuit receives first clock information associated with a first clock of another electronic device. The clock generator circuit generates a second clock for the electronic device. The clock control circuit obtains second clock information associated with the second clock, generates a clock control signal according to the first clock information and the second clock information, and outputs the clock control signal to the clock generator circuit, where the clock generator circuit adjusts the second clock in response to the clock control signal.