Clock Control Circuit for Dynamic Frequency Restoration in Multi-Core Processors
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Solution Overview
Problem
In semiconductor devices with multiple processor cores sharing a common power supply, the Adaptive Clocking Control (ACC) mechanism can lead to prolonged performance deterioration due to frequent reactivation of clock frequency adjustments in response to power supply voltage drops, as uniform and slow restoration of clock frequencies can cause repeated drops in power supply voltage, leading to intermittent performance degradation.
Innovation Solution
Each processor core in the semiconductor device includes a clock control circuit that adjusts the speed of clock frequency restoration based on the power supply voltage and clock frequency situations of other processor cores, allowing for dynamic adjustment to avoid reactivation of the ACC by selecting the fastest restoration speed within a range that prevents power supply voltage drops, thereby shortening the duration of performance deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is rapidly increased after power supply voltage recovery, then the performance deterioration due to frequency decrease is suppressed, but the power supply voltage may drop again due to rapid current increase
Solution Approach 1:
The patent applies dynamics by making the clock frequency restoration speed adjustable rather than fixed. The clock control circuit dynamically changes the restoration speed based on the operating states of other processor cores, allowing the system to adapt between rapid restoration (for performance) and controlled restoration (for stability) as conditions change.
Solution Approach 2:
The patent implements feedback by having each clock control circuit monitor the power supply voltage situations and clock frequency states of other processor cores. This feedback information is used to adjust the restoration speed of the own core's clock frequency, creating a closed-loop control system that prevents voltage drops while recovering performance.
2Reliability
If the clock frequency is increased at a uniform slow speed across all cores, then power supply voltage drops are avoided, but the duration of performance deterioration is prolonged
Solution Approach 1:
The patent applies local quality by allowing each processor core to have a different clock frequency restoration speed based on its local situation and the situations of other cores. Instead of a uniform restoration speed for all cores, each core adjusts its restoration speed independently according to the overall system state, optimizing both stability and recovery time.
Solution Approach 2:
The restoration speed is made dynamic rather than static. The clock control circuit continuously adjusts the restoration speed based on real-time monitoring of power supply voltage and clock frequency states, enabling the system to transition from slow uniform restoration to faster differentiated restoration as conditions permit.
3Reliability
If the ACC is frequently reactivated due to premature frequency restoration, then timing errors are prevented, but intermittent performance degradation occurs
Solution Approach 1:
The patent applies preliminary action by having each clock control circuit proactively monitor the states of other processor cores and adjust its own frequency restoration speed in advance. This preventive approach allows the system to avoid voltage drops before they occur, preventing ACC reactivation rather than reacting to it after the fact, thus maintaining both timing accuracy and performance continuity.
Data Source
AI summary
A semiconductor device includes a power supply; and a plurality of processor cores configured to operate with the power supply, wherein each of the plurality of processor cores includes a clock control circuit that decreases an own clock frequency used by an own processor core when detecting drop of a power supply voltage of the own processor core, and adjusts a speed at which the own clock frequency is increased according to a situation of a power supply voltage of another processor core among the plurality of processor cores.